SH7059 Datasheet, PDF (300/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
• Bit 0—Input Capture/Compare-Match Flag 2A (IMF2A): Status flag that indicates GR2A input capture or compare-
match.
Bit 0: IMF2A
0
1
Description
[Clearing condition]
When IMF2A is read while set to 1, then 0 is written to IMF2A
(Initial value)
[Setting conditions]
• When the TCNT2A value is transferred to GR2A by an input capture signal while GR2A
is functioning as an input capture register
• When TCNT2A = GR2A while GR2A is functioning as an output compare register
TSR2B: TSR2B indicates the status of channel 2 compare-match and overflow.
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
OVF2B
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/(W)*
Bit:
Initial value:
R/W:
7
CMF2H
0
R/(W)*
6
CMF2G
0
R/(W)*
5
CMF2F
0
R/(W)*
Note: * Only 0 can be written to clear the flag.
4
CMF2E
0
R/(W)*
3
CMF2D
0
R/(W)*
2
CMF2C
0
R/(W)*
1
CMF2B
0
R/(W)*
0
CMF2A
0
R/(W)*
• Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 8—Overflow Flag 2B (OVF2B): Status flag that indicates TCNT2B overflow.
Bit 8: OVF2B
0
1
Description
[Clearing condition]
When OVF2B is read while set to 1, then 0 is written to OVF2B
[Setting condition]
When the TCNT2B value overflows (from H'FFFF to H'0000)
(Initial value)
• Bit 7—Compare-Match Flag 2H (CMF2H): Status flag that indicates OCR2H compare-match.
Bit 7: CMF2H
0
1
Description
[Clearing condition]
When CMF2H is read while set to 1, then 0 is written to CMF2H
[Setting condition]
When TCNT2B = OCR2H
(Initial value)
Rev.3.00 Mar. 12, 2008 Page 210 of 948
REJ09B0177-0300