SH7059 Datasheet, PDF (13/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H)
7.1.2 Block Diagram
Figure 7.1 INTC Block Diagram
102
7.2.5 On-Chip Peripheral Module Interrupts
105
7.2.6 Interrupt Exception Vectors and Priority Rankings
Table 7.3 Interrupt Exception Processing Vectors and
Priorities
113, 114
Interrupt Source
Interrupt Source
SCI0
ERI0
RXI0
TXI0
SCI2
ERI2
RXI2
TXI2
SH7058S/SH7059
7.1.2 Block Diagram
Figure 7.1 INTC Block Diagram
SSU interrupt request added to CPU/DMAC request
judgment
7.2.5 On-Chip Peripheral Module Interrupts
Synchronous communication unit (SSU) added
7.2.6 Interrupt Exception Vectors and Priority Rankings
Table 7.3 Interrupt Exception Processing Vectors and
Priorities
Interrupt Source: SSU added
Interrupt Source
SCI0/
SSU0*
SCI2/
SSU1*
ERI0/
SSERI0
RXI0/
SSRXI0
TXI0/
SSTSI0
ERI2/
SSERI1
RXI2/
SSRXI1
TXI2/
SSTSI1
7.3.1 Interrupt Priority Registers A–L (IPRA–IPRL)
Table 7.4 Interrupt Request Sources and IPRA–IPRL
116
Bits
Register
15–12
7–4
Interrupt priority register K
SCI0
SCI2
7.3.1 Interrupt Priority Registers A–L (IPRA–IPRL)
Table 7.4 Interrupt Request Sources and IPRA–IPRL
Table amended
Register
Interrupt priority register K
15–12
SCI0/SSU0*
Bits
7–4
SCI2/SSU1*
7.3.1 Interrupt Priority Registers A–L (IPRA–IPRL)
116
If multiple on-chip peripheral modules are assigned to the
same bit (DMAC0 and DMAC1, DMAC2 and DMAC3,
CMT0, A/D0, and MTAD0, and CMT1, A/D1, and MTAD1),
those multiple modules are set to the same priority rank.
IPRA–IPRL are initialized to H'0000 by a reset and in
hardware standby mode. They are not initialized in
software standby mode.
7.3.3 IRQ Status Register (ISR)
118
A reset and hardware standby mode initialize ISR but
software standby mode does not.
7.3.1 Interrupt Priority Registers A–L (IPRA–IPRL)
Description amended
If multiple on-chip peripheral modules are assigned to the
same bit (DMAC0 and DMAC1, DMAC2 and DMAC3,
CMT0, A/D0, and MTAD0, CMT1, A/D1, and MTAD1, SCI0
and SSU0*, and SCI2 and SSU1*), those multiple modules
are set to the same priority rank.
IPRA–IPRL are initialized to H'0000 by a reset, in hardware
standby mode and in software standby mode.
7.3.3 IRQ Status Register (ISR)
Description amended
A reset, hardware standby mode and software standby
mode initialize ISR .
Rev.3.00 Mar. 12, 2008 Page xiii of xc
REJ09B0177-0300