SH7059 Datasheet, PDF (362/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
Input Capture Register 10AH, AL (ICR10AH, ICR10AL): Input capture register 10AH, AL (comprising ICR10AH
and ICR10AL) is a 32-bit read-only register to which the TCNT10AH, AL value is transferred on external input (TI10)
(AGCK). At the same time, ICF10A in timer status register 10 (TSR10) is set to 1.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
ICR10A is initialized to H'00000000 by a power-on reset, and in hardware standby mode and software standby mode.
Output Compare Register 10AH, AL (OCR10AH, OCR10AL): Output compare register 10AH, AL (comprising
OCR10AH and OCR10AL) is a 32-bit readable/writable register that is constantly compared with free-running counter
10AH, AL (TCNT10AH, TCNT10AL). When both values match, CMF10A in timer status register 10 (TSR10) is set to 1.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
OCR10A is initialized to H'FFFFFFFF by a power-on reset, and in hardware standby mode and software standby mode.
Output Compare Register 10B (OCR10B): Output compare register 10B (OCR10B) is an 8-bit readable/writable
register that is constantly compared with free-running counter 10B (TCNT10B). When AGCK is input with both values
matching, CMF10B in timer status register 10 (TSR10) is set to 1.
Bit:
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OCR10B is initialized to H'FF by a power-on reset, and in hardware standby mode and software standby mode.
Reload Register 10C (RLD10C): Reload register 10C (RLD10C) is a 16-bit readable/writable register. When STR10 in
timer start register 1 (TSTR1) is 1 and RLDEN in the timer I/O control register (TIOR10) is 0, and the value of TCNT10A
is captured into input capture register 10A (ICR10A), the ICR10A capture value is shifted according to the multiplication
factor set by bits PIM1 and PIM0 in TIOR10 before being transferred to RLD10C. The contents of reload register 10C
(RLD10C) are loaded when reload counter 10C (TCNT10C) reaches H'0001.
Rev.3.00 Mar. 12, 2008 Page 272 of 948
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