SH7059 Datasheet, PDF (672/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. Pin Function Controller (PFC)
• Bit 3—Reserved: This bit is always read as 0. The write value should always be 0.
• Bit 2—PA1 Mode Bit (PA1MD): Selects the function of pin PA1/TI0B.
Bit 2: PA1MD
0
1
Description
General input/output (PA1)
ATU-II input capture input (TI0B)
• Bit 1—Reserved: This bit is always read as 0. The write value should always be 0.
• Bit 0—PA0 Mode Bit (PA0MD): Selects the function of pin PA0/TI0A.
Bit 0: PA0MD
0
1
Description
General input/output (PA0)
ATU-II input capture input (TI0A)
(Initial value)
(Initial value)
22.3.3 Port B IO Register (PBIOR)
Bit: 15
14
13
12
11
10
9
8
PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8
IOR
IOR
IOR
IOR
IOR
IOR
IOR
IOR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
IOR
IOR
IOR
IOR
IOR
IOR
IOR
IOR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The port B IO register (PBIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins
in port B. Bits PB15IOR to PB0IOR correspond to pins PB15/PULS5/SCK2/SSCK1 to PB0/TO6A. PBIOR is enabled
when port B pins function as general input/output pins (PB15 to PB0) or serial clock pins (SCK0, SCK1, SCK2, SSCK0,
SSCK1), and disabled otherwise.
When port B pins function as PB15 to PB0 or SCK0, SCK1, and SCK2, SSCK0, SSCK1, a pin becomes an output when
the corresponding bit in PBIOR is set to 1, and an input when the bit is cleared to 0.
PBIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in
software standby mode. It is not initialized in sleep mode.
22.3.4 Port B Control Registers H and L (PBCRH, PBCRL)
Port B control registers H and L (PBCRH, PBCRL) are 16-bit readable/writable registers that select the functions of the 16
multiplex pins in port B. PBCRH selects the functions of the pins for the upper 8 bits of port B, and PBCRL selects the
functions of the pins for the lower 8 bits.
PBCRH and PBCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware
standby mode and in software standby mode. They are not initialized in sleep mode.
Rev.3.00 Mar. 12, 2008 Page 582 of 948
REJ09B0177-0300