SH7059 Datasheet, PDF (746/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

24. ROM (SH7058S)
24.4.3 Programming/Erasing Interface Parameters
The programming/erasing interface parameters specify the operating frequency, user branch destination address, storage
place for program data, programming destination address, and erase block and exchanges the processing result for the
downloaded on-chip program. This parameter uses the general registers of the CPU (R4, R5, and R0) or the on-chip RAM
area. The initial value is undefined at a power-on reset, in hardware standby mode, or in software standby mode.
At download all CPU registers are stored, and at initialization or when the on-chip program is executed, CPU registers
except for R0 are stored. The return value of the processing result is written in R0. Since the stack area is used for storing
the registers or as a work area, the stack area must be saved at the processing start. (The maximum size of a stack area to
be used is 128 bytes.)
The programming/erasing interface parameters are used in the following four items.
(1) Download control
(2) Initialization before programming or erasing
(3) Programming
(4) Erasing
These items use different parameters. The correspondence table is shown in table 24.6.
The processing results of initialization, programming, and erasing are returned, but the bit contents have different
meanings according to the processing program. See the description of FPFR for each processing.
Table 24.6 Usable Parameters and Target Modes
Name of
Parameter
Abbreviation Down-load
Initiali-
zation
Pro-
gram-
ming Erasure R/W
Download DPFR
O
pass/fail result
—
—
—
R/W
Flash pass/fail FPFR
—
result
O
O
O
R/W
Flash
FPEFEQ
—
programming/
erasing
frequency
control
O
—
—
R/W
Flash user FUBRA
—
branch
address set
parameter
O
—
—
R/W
Flash
FMPAR
—
multipurpose
address area
—
O
—
R/W
Flash
FMPDR
—
multipurpose
data
destination
area
—
O
—
R/W
Flash erase FEBS
—
block select
—
—
O
R/W
Note: * One byte of start address of download destination specified by FTDAR
Initial Value Allocation
Undefined On-chip
RAM*
Undefined R0 of CPU
Undefined R4 of CPU
Undefined R5 of CPU
Undefined R5 of CPU
Undefined R4 of CPU
Undefined R4 of CPU
Rev.3.00 Mar. 12, 2008 Page 656 of 948
REJ09B0177-0300