SH7059 Datasheet, PDF (282/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
• Bits 5 and 4—Edge Select B1, B0, D1, D0, F1, F0 (EGSELB1, EGSELB0, EGSELD1, EGSELD0, EGSELF1,
EGSELF0): These bits select the event counter counted edge(s).
Bit 5: EGSELx1 Bit 4: EGSELx0
0
0
1
1
0
1
Note: x = B, D, or F
Description
Count disabled
Rising edges counted
Falling edges counted
Both rising and falling edges counted
(Initial value)
• Bit 3—Reserved: This bit is always read as 0. The write value should always be 0.
• Bit 2—Trigger Channel 3AEN, 3CEN (TRG3AEN, TRG3CEN): These bits select the channel 9 event counter
compare-match signal channel 3 input capture trigger.
Bit 2: TRG3xEN
0
1
Note: x = A or C
Description
Channel 3 input capture trigger in event of channel 9 compare-match (ECNT9x = GR9x) is
disabled
(Initial value)
Channel 3 input capture trigger in event of channel 9 compare-match (ECNT9x = GR9x) is
enabled
• Bits 1 and 0—Edge Select A1, A0, C1, C0, E1, E0 (EGSELA1, EGSELA0, EGSELC1, EGSELC0, EGSELE1,
EGSELE0): These bits select the event counter counted edge(s).
Bit 1: EGSELx1 Bit 0: EGSELx0
0
0
1
1
0
1
Note: x = A, C, or E
Description
Count disabled
Rising edges counted
Falling edges counted
Both rising and falling edges counted
(Initial value)
Timer Control Register 11 (TCR11)
Bit:
7
6
—
—
Initial value:
0
0
R/W:
R
R
5
CKEG1
0
R/W
4
CKEG0
0
R/W
3
2
1
0
—
CKSELA2 CKSELA1 CKSELA0
0
0
0
0
R
R/W
R/W
R/W
• Bits 7, 6, and 3—Reserved: These bits are always read as 0. The write value should always be 0.
• Bits 5 and 4—Edge Select: These bits select the event counter counted edge(s).
Bit 5: CKEG1
0
1
Bit 4: CKEG0
0
1
0
1
Description
Rising edges counted
Falling edges counted
Both rising and falling edges counted
Count disabled
(Initial value)
Rev.3.00 Mar. 12, 2008 Page 192 of 948
REJ09B0177-0300