SH7059 Datasheet, PDF (294/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
• Bit 1—Input Capture Flag 0B (ICF0B): Status flag that indicates ICR0B input capture.
Bit 1: ICF0B
0
1
Description
[Clearing condition]
When ICF0B is read while set to 1, then 0 is written to ICF0B
(Initial value)
[Setting condition]
When the TCNT0 value is transferred to the input capture register by an input capture signal
• Bit 0—Input Capture Flag 0A (ICF0A): Status flag that indicates ICR0A input capture.
Bit 0: ICF0A
0
1
Description
[Clearing condition]
When ICF0A is read while set to 1, then 0 is written to ICF0A
(Initial value)
[Setting condition]
When the TCNT0 value is transferred to the input capture register by an input capture signal
Timer Status Registers 1A and 1B (TSR1A, TSR1B)
TSR1A: TSR1A indicates the status of channel 1 input capture, compare-match, and overflow.
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
OVF1A
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/(W)*
Bit:
Initial value:
R/W:
7
IMF1H
0
R/(W)*
6
IMF1G
0
R/(W)*
5
IMF1F
0
R/(W)*
Note: * Only 0 can be written, to clear the flag.
4
IMF1E
0
R/(W)*
3
IMF1D
0
R/(W)*
2
IMF1C
0
R/(W)*
1
IMF1B
0
R/(W)*
0
IMF1A
0
R/(W)*
• Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 8—Overflow Flag 1A (OVF1A): Status flag that indicates TCNT1A overflow.
Bit 8: OVF1A
0
1
Description
[Clearing condition]
When OVF1A is read while set to 1, then 0 is written to OVF1A
[Setting condition]
When the TCNT1A value overflows (from H'FFFF to H'0000)
(Initial value)
Rev.3.00 Mar. 12, 2008 Page 204 of 948
REJ09B0177-0300