SH7059 Datasheet, PDF (78/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9.2.3 Wait Control Register (WCR)................................................................................................................... 117
9.2.4 RAM Emulation Register (RAMER)........................................................................................................ 119
9.3 Accessing External Space ...................................................................................................................................... 121
9.3.1 Basic Timing............................................................................................................................................. 121
9.3.2 Wait State Control .................................................................................................................................... 122
9.3.3 CS Assert Period Extension ...................................................................................................................... 123
9.4 Waits between Access Cycles................................................................................................................................ 123
9.4.1 Prevention of Data Bus Conflicts.............................................................................................................. 123
9.4.2 Simplification of Bus Cycle Start Detection ............................................................................................. 124
9.5 Bus Arbitration....................................................................................................................................................... 125
9.6 Memory Connection Examples.............................................................................................................................. 126
Section 10 Direct Memory Access Controller (DMAC) .................................................................. 129
10.1 Overview................................................................................................................................................................ 129
10.1.1 Features..................................................................................................................................................... 129
10.1.2 Block Diagram.......................................................................................................................................... 130
10.1.3 Register Configuration.............................................................................................................................. 130
10.2 Register Descriptions ............................................................................................................................................. 132
10.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) ............................................................................... 132
10.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3)....................................................................... 132
10.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3).............................................................. 133
10.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)........................................................................ 134
10.2.5 DMAC Operation Register (DMAOR) ..................................................................................................... 137
10.3 Operation ............................................................................................................................................................... 138
10.3.1 DMA Transfer Flow ................................................................................................................................. 138
10.3.2 DMA Transfer Requests ........................................................................................................................... 140
10.3.3 Channel Priority........................................................................................................................................ 143
10.3.4 DMA Transfer Types................................................................................................................................ 143
10.3.5 Dual Address Mode .................................................................................................................................. 144
10.3.6 Bus Modes ................................................................................................................................................ 148
10.3.7 Relationship between Request Modes and Bus Modes by DMA Transfer Category................................ 149
10.3.8 Bus Mode and Channel Priorities ............................................................................................................. 149
10.3.9 Source Address Reload Function.............................................................................................................. 150
10.3.10 DMA Transfer Ending Conditions............................................................................................................ 151
10.3.11 DMAC Access from CPU......................................................................................................................... 151
10.4 Examples of Use .................................................................................................................................................... 152
10.4.1 Example of DMA Transfer between On-Chip SCI and External Memory ............................................... 152
10.4.2 Example of DMA Transfer between A/D Converter and On-Chip Memory (Address Reload On) ......... 152
10.4.3 Example of DMA Transfer between External Memory and SCI1 Transmitting Side
(Indirect Address on) ................................................................................................................................ 154
10.5 Usage Notes ........................................................................................................................................................... 155
Section 11 Advanced Timer Unit-II (ATU-II) ................................................................................. 157
11.1 Overview................................................................................................................................................................ 157
11.1.1 Features..................................................................................................................................................... 157
11.1.2 Pin Configuration...................................................................................................................................... 161
11.1.3 Register Configuration.............................................................................................................................. 164
11.1.4 Block Diagrams ........................................................................................................................................ 170
11.1.5 Inter-Channel and Inter-Module Signal Communication Diagram........................................................... 180
11.1.6 Prescaler Diagram..................................................................................................................................... 181
11.2 Register Descriptions ............................................................................................................................................. 182
11.2.1 Timer Start Registers (TSTR) ................................................................................................................... 182
Rev.3.00 Mar. 12, 2008 Page lxxviii of xc
REJ09B0177-0300