SH7059 Datasheet, PDF (624/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Multi-Trigger A/D Converter (MTAD)
19.3.7 Operation Waveform Examples
(A)
Hardware Operation
1. A compare match occurs, setting the status flag to the corresponding source.
2. Multi-trigger A/D conversion that is enabled by A/D trigger (ADTRG) in the A/D trigger interrupt enable register
(ADTIER) starts.
After Multi-trigger A/D conversion is Over
3. Multi-trigger A/D conversion result is transferred to the register that is specified by A/D select (ADSEL) in the A/D
trigger control register (ADTCR) at the start of the conversion.
4. An interrupt is generated if the multi-trigger A/D conversion end interrupt is enabled.
Software Operation
1. A compare match flag is cleared.
2. The value in the A/D general register (ADGR) is changed.
3. A/D select (ADSEL) in the A/D trigger control register (ADTCR) is changed.
After Multi-trigger A/D conversion is Over
4. The multi-trigger A/D conversion end flag is cleared.
5. The conversion result is read out.
(B)
Hardware Operation
1. A compare match occurs, setting the status flag to the corresponding source.
2. An interrupt is generated if the A/D duty enable bit (ADDE) in the A/D trigger interrupt enable register (ADTIER) is
set.
3. The level of the external output pin is changed.
Software Operation
1. The duty compare match flag is cleared.
(C)
Hardware Operation
1. A compare match occurs, setting the status flag to the corresponding source.
2. An interrupt is generated if the A/D cycle enable bit (ADCYLR) in the A/D trigger interrupt enable register (ADTIER)
is set.
3. The level of the external output pin is changed.
4. Clear ADCNT to H'0001
Software Operation
1. The cycle compare match flag is cleared.
2. The values in the A/D duty register (ADDR) and the A/D cycle register (ADCYLR) are changed.
Rev.3.00 Mar. 12, 2008 Page 534 of 948
REJ09B0177-0300