SH7059 Datasheet, PDF (536/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
Bit
Bit Name Initial Value R/W Description
12
IRR12
0
R/W Bus Activity Interrupt Flag
Indicates that a CAN bus activity is present. While the HCAN is in sleep
mode and a recessive to dominant bit transition takes place on the CAN bus,
this bit is set. The operation of this interrupt is set in the master control
register (MCR7: Auto-wake mode). This interrupt is cleared by writing a 1 to
this bit. Writing a 0 is ignored.
0: Bus idle state
Clearing condition: Writing 1
1: CAN bus activity detected in HCAN sleep mode
Setting condition: Recessive → dominant bit transition detection while in
sleep mode
11
IRR11
0
R/W Timer Compare Match Interrupt Flag 2
Indicates that a compare-match condition occurred to the timer compare
match register 2 (TCMR2). When the value set in TCMR2 matches the timer
value (TCMR2 = TCNTR) or matches Cycle_Count + TCNTR[15:4]
depending on the TMR2 (timer mode register) setting, this bit is set. This bit
is not set if the TCMR2 value is H'0000.
0: Timer compare match has not occurred to TCMR2
Clearing condition: Writing 1
1: Timer compare match has occurred to TCMR2
Setting condition: TCMR2 matches the timer value (TCMR2 = TCNTR) if
TMR2 = 0 or matches Cycle_Count + TCNTR[15:4] if TMR2 = 1
10
IRR10
0
R/W Cycle Counter Overrun Interrupt Flag
Indicates that the Cycle_Counter has reached the maximum value (CMAX).
When the CCR counter matches the CMAX value (CCR = CMAX), this bit is
set and CCR is cleared. Note that setting CMAX = 0 disables the
Cycle_Counter and no interrupt is generated.
0: Cycle counter has not reached CMAX or CMAX = 0
Clearing condition: Writing 1
1: Cycle counter has reached CMAX and CMAX ≠ 0
Setting condition: CCR matches the CMAX value (CCR = CMAX)
9
IRR9
0
R
Message Overrun/Overwrite Interrupt Flag
Status flag indicating that new message has been received but the existing
message in the mailbox has not been read due to the corresponding RXPR
or RFPR set to 1. The received message is either abandoned (overrun) or
overwritten dependant upon the NMC (new message control) bit. This bit is
cleared by writing 1 to the correspondent bit in UMSR (unread message
status register). Writing 0 is ignored.
0: No message overrun/overwrite
Clearing condition: Clearing of all bits in UMSR
1: Receive message overrun and its storage has been rejected or message
overwrite
Setting condition: Message is received while the corresponding RXPR or
RFPR = 1 and MBIMR = 0
Rev.3.00 Mar. 12, 2008 Page 446 of 948
REJ09B0177-0300