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| SH7059 Datasheet, PDF (72/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer | |||
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Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H)
SH7058S/SH7059
Appendix B Pin States
Table B.1 Pin States
1079, 1080
Type Pin Name
Clock CK*2
XTAL
EXTAL
PLLCAP
System RES
control FWE
HSTBY
MD0
MD1
MD2
WDTOVF
BREQ
BACK
Interrupt NMI
IRQ0 to IRQ7
IRQOUT
Address A0 to A21
bus
Data bus D0 to D7
Bus
control
D8 to D15
WAIT
WRH, WRL
RD
CS0
CS1 to CS3
Port POD
ATU-II TI0A to TI0D
TIO1A to TIO1H
TIO2A to TIO2H
TIO3A to TIO3D
Pin State
Reset State
Power-Down State
Power-On
ROMless
Expanded Mode
8 Bits 16 Bits
Expanded Single-
H-UDI
Mode with Chip Hardware Software Module
ROM
Mode Standby Standby Standby
AUD
Module
Standby
Bus-Relea
sed State
O
Z
H*1
O
O
O
O
L
L
O
O
O
I
Z
I
I
I
I
I
I
I
I
I
I
I
Z
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
Z
O*1
O
O
O
â
Z
Z
I
I
I
â
Z
Z
O
O
L
I
Z
I
I
I
I
â
Z
Z
I
I
I
â
Z
O*1
O
O
O
O
â
Z
Z
O
O
Z
Z
â
â
Z
â
I
H
H
H
â
â
â
â
â
â
Z
Z
â
Z
â
Z
â
Z
â
Z
Z
Z
Z
Z
Z
Z
Z
I/O
I/O
Z
Z
I/O
I/O
Z
Z
I
I
I
Z
O
O
Z
Z
O
O
Z
Z
O
O
Z
Z
O
O
Z
Z
I
I
I
Z
I
I
I
K*1
I/O
I/O
I/O
K*1
I/O
I/O
I/O
K*1
I/O
I/O
I/O
Appendix B Pin States
Table B.1 Pin States
Table amended
Type
Pin Name
Clock
CK*1
XTAL
EXTAL
System
control
PLLCAP
RES
FWE
HSTBY
MD0
MD1
MD2
WDTOVF
BREQ
BACK
Interrupt
NMI
IRQ0 to IRQ7
IRQOUT
Address bus A0 to A21
Data bus D0 to D7
Bus
control
D8 to D15
WAIT
WRH, WRL
RD
CS0
CS1 to CS3
Port
POD
ATU-II
TI0A to TI0D
TIO1A to TIO1H
TIO2A to TIO2H
TIO3A to TIO3D
Reset State
Power-On
ROMless
Expanded Mode
8 Bits 16 Bits
Expanded
Mode with
ROM
O
I/O
I
I
I
I
I
I
I
I
O
â
â
I
â
â
O
â
Z
â
â
Z
â
I
â
H
â
H
â
H
â
â
â
â
â
â
â
Pin State
Power-Down State
Single-Chi
p Mode Hardware
Standby
Z
L
Z
I
Z
I
I
I
I
I
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Software
Standby
Z
L
Z
I
I
I
I
I
I
I
Z
Z
Z
I
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
H-UDI
Module
Standby
O
I/O
I
I
I
I
I
I
I
I
O
I
O
I
I
O
O
I/O
I/O
I
O
O
O
O
I
I
I/O
I/O
I/O
AUD Module Bus-Release
Standby d State
O
O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
I
I
O
L
I
I
I
I
O
O
O
Z
I/O
Z
I/O
Z
I
I
O
Z
O
Z
O
Z
O
Z
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
Pin State
Reset State
Power-Down State
Power-On
Type Pin Name
ROMless
Expanded Mode
8 Bits 16 Bits
Expanded Single-
H-UDI
Mode with Chip Hardware Software Module
ROM
Mode Standby Standby Standby
AUD
Module
Standby
Bus-Relea
sed State
ATU-II TIO4A to TIO4D â
TIO5A to TIO5D â
TO6A to TO6D â
TO7A to TO7D â
TO8A to TO8P â
Z
K*1
I/O
I/O
I/O
Z
K*1
I/O
I/O
I/O
Z
O*1
O
O
O
Z
O*1
O
O
O
Z
O*1
O
O
O
TI9A to TI9F
â
Z
Z
I
I
I
TI10
â
TIO11A, TIO11B â
Z
Z
I
I
I
Z
K*1
I/O
I/O
I/O
TCLKA, TCLKB â
SCI
SCK0 to SCK4 â
TxD0 to TxD4
â
Z
Z
I
I
I
Z
K*1
I/O
I/O
I/O
Z
O*1
O
O
O
RxD0 to RxD4 â
Z
Z
I
I
I
A/D
AN0 to AN31
Z
converter ADTRG0,
â
ADTRG1
ADEND
â
Z
Z
I
I
I
Z
Z
I
I
I
Z
O*1
O
O
O
APC
HCAN
AVref
I
PULS0 to PULS7 â
HTxD0, HTxD1 â
I
I
I
I
I
Z
O*1
O
O
O
Z
O*1
O
O
O
HRxD0, HRxD1 â
UBC UBCTRG
â
I/O
PA0 to PA15
Z
port
PB0 to PB15
Z
PC0 to PC4
Z
PD0 to PD13
Z
PE0 to PE15
â
Z
PF0 to PF5
â
Z
PF6 to PF10
â
PH11 to PF15 Z
PG0 to PG3
Z
PH0 to PH7
â
Z
PH8 to PH15
Z
â
Z
PJ0 to PJ15
Z
PK0 to PK15
Z
PL0 to PL13
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
I
I
I
O*1
O
O
O
K*1
I/O
I/O
I/O
K*1
I/O
I/O
I/O
K*1
I/O
I/O
I/O
K*1
I/O
I/O
I/O
K*1
I/O
I/O
I/O
K*1
I/O
I/O
I/O
K*1
I/O
I/O
I/O
K*1
I/O
I/O
I/O
K*1
I/O
I/O
I/O
K*1
I/O
I/O
I/O
K*1
I/O
I/O
I/O
K*1
I/O
I/O
I/O
K*1
I/O
I/O
I/O
K*1
I/O
I/O
I/O
Type
ATU-II
SCI
A/D
converter
MTAD
APC
HCAN
UBC
I/O
port
SSU*2
Pin Name
TIO4A to TIO4D
TIO5A to TIO5D
TO6A to TO6D
TO7A to TO7D
TO8A to TO8P
TI9A to TI9F
TI10
TIO11A, TIO11B
TCLKA, TCLKB
SCK0 to SCK4
TxD0 to TxD4
RxD0 to RxD4
AN0 to AN31
ADTRG0,
ADTRG1
ADEND
AVref
ADTO0A
ADTO0B
ADTO1A
ADTO1B
PULS0 to PULS7
HTxD0, HTxD1
HRxD0, HRxD1
UBCTRG
PA0 to PA15
PB0 to PB15
PC0 to PC4
PD0 to PD13
PE0 to PE15
PF0 to PF5
PF6 to PF10
PH11 to PF15
PG0 to PG3
PH0 to PH7
PH8 to PH15
PJ0 to PJ15
PK0 to PK15
PL0 to PL13
SSCK0, SSCK1
SSI0, SSI1
SSO0, SSO1
SCS0, SCS1
Reset State
Power-On
ROMless
Expanded Mode
8 Bits 16 Bits
Expanded
Mode with
ROM
â
â
â
â
â
â
â
â
â
â
â
â
Z
â
Pin State
Power-Down State
Single-Chi
p Mode Hardware
Standby
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Software
Standby
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
H-UDI
Module
Standby
I/O
I/O
O
O
O
I
I
I/O
I
I/O
O
I
I
I
AUD Module Bus-Release
Standby d State
I/O
I/O
I/O
I/O
O
O
O
O
O
O
I
I
I
I
I/O
I/O
I
I
I/O
I/O
O
O
I
I
I
I
I
I
â
I
â
â
â
â
â
â
â
â
Z
Z
Z
Z
â
Z
â
Z
â
Z
Z
â
Z
Z
â
Z
Z
Z
Z
â
â
â
â
Z
Z
O
O
O
I
I
I
I
I
Z
Z
O
O
O
Z
Z
O
O
O
Z
Z
O
O
O
Z
Z
O
O
O
Z
Z
O
O
O
Z
Z
O
O
O
Z
Z
I
O
I
Z
Z
O
O
O
Z
Z
I/O
I/O
I/O
Z
Z
I/O
I/O
I/O
Z
Z
I/O
I/O
I/O
Z
Z
I/O
I/O
I/O
Z
Z
I/O
I/O
I/O
Z
Z
I/O
I/O
I/O
Z
Z
Z
I/O
I/O
I/O
Z
Z
I/O
I/O
I/O
Z
Z
I/O
I/O
I/O
Z
Z
I/O
I/O
I/O
Z
Z
I/O
I/O
I/O
Z
Z
I/O
I/O
I/O
Z
Z
I/O
I/O
I/O
Z
Z
I/O
I/O
I/O
Z
Z
O
O
O
Z
Z
I
I
I
Z
Z
O
O
O
Z
Z
I/O
I/O
I/O
Rev.3.00 Mar. 12, 2008 Page lxxii of xc
REJ09B0177-0300
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