SH7059 Datasheet, PDF (911/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

27. Power-Down State
27.5 Sleep Mode
27.5.1 Transition to Sleep Mode
Executing the SLEEP instruction after the software standby bit (SSBY) in SBYCR has been cleared to 0 causes a
transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral modules continue to run
during sleep mode.
27.5.2 Canceling Sleep Mode
Cancellation by Interrupt: When an interrupt occurs, sleep mode is canceled and interrupt exception processing is
executed. The sleep mode is not canceled if the interrupt cannot be accepted because its priority level is equal to or less
than the mask level set in the CPU's status register (SR) or if an interrupt by an on-chip peripheral module is disabled by
the peripheral module.
Cancellation by DMA Address Error: If a DMA address error occurs, sleep mode is canceled and DMA address error
exception processing is executed.
Cancellation by Manual Reset: When an internal manual reset is triggered by the WDT and the CPU acquires the bus
during the internal manual reset period, the state of this LSI changes to the manual reset state and sleep mode will be
released.
Cancellation by Power-On Reset: A power-on reset of this LSI resulting from driving the RES pin low, or caused by the
WDT, cancels sleep mode.
Note: When performing cancellation by power-on reset, do not place RAM write instructions immediately (within eight
instructions) after the sleep instruction. This will ensure that no instructions are executed before the transition to
the reset.
Rev.3.00 Mar. 12, 2008 Page 821 of 948
REJ09B0177-0300