SH7059 Datasheet, PDF (356/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
General Registers 9A to 9F (GR9A to GR9F)
Bit:
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
These GR registers are 8-bit readable/writable registers with a compare-match function.
The GR value and event counter (ECNT) value are constantly compared, and when both values match a compare-match
signal is generated and the next edge is input, the corresponding CMF bit in TSR is set to 1.
In addition, channel 3 (GR3A to GR3D) input capture can be generated by GR9A to GR9D compare-matches. This
function is set by TRG3xEN in the timer control register (TCR).
The GR registers can be accessed by a byte read or write.
The GR registers are initialized to H'FF by a power-on reset, and in hardware standby mode and software standby mode.
11.2.21 Offset Base Registers (OSBR)
The offset base registers (OSBR) are 16-bit registers. The ATU-II has two OSBR registers, one each in channels 1 and 2.
Channel Abbreviation Function
1
OSBR1
Dedicated input capture registers with the same input trigger signal as that for channel 0 ICR0A
2
OSBR2
Offset Base Registers 1 and 2 (OSBR1, OSBR2)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
OSBR1 and OSBR2 are 16-bit read-only registers used exclusively for input capture. OSBR0 and OSBR1 use the same
input trigger signal (TI0A) as that for the channel 0 input capture register (ICR0A), and store the TCNT1A or TCNT2A
value on detection of an edge.
The OSBR registers can only be accessed by a word read.
The OSBR registers are initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby
mode.
For details, see sections 11.3.8, Twin-Capture Function.
Rev.3.00 Mar. 12, 2008 Page 266 of 948
REJ09B0177-0300