SH7059 Datasheet, PDF (541/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
17.5 HCAN Mailbox Registers
The HCAN mailbox registers control individual mailboxes. The address is mapped as follows.
Note: These registers can only be accessed in word size (16 bits).
Table 17.6 HCAN Mailbox Registers
Channel
0
Address (Bytes)
H'D020
H'D022
H'D024
H'D026
H'D028
H'D02A
H'D02C
H'D02E
H'D030
H'D032
H'D034
H'D036
H'D038
H'D03A
H'D03C
H'D03E
H'D040
H'D042
H'D044
H'D046
H'D048
H'D04A
H'D04C
H'D04E
H'D050
H'D052
H'D054
H'D056
H'D058
H'D05A
H'D05C
H'D05E
Register Name
Transmit wait register 1_0
Transmit wait register 0_0
Transmit wait cancel register 1_0
Transmit wait cancel register 0_0
Transmit acknowledge register 1_0
Transmit acknowledge register 0_0
Abort acknowledge register 1_0
Abort acknowledge register 0_0
Received complete register 1_0
Received complete register 0_0
Remote request register 1_0
Remote request register 0_0
Mailbox interrupt mask register 1_0
Mailbox interrupt mask register 0_0
Unread message status register 1_0
Unread message status register 0_0
Abbreviation
R/W
TXPR1_0
R/W
TXPR0_0
R/W
TXCR1_0
R/W
TXCR0_0
R/W
TXACK1_0
R/W
TXACK0_0
R/W
ABACK1_0
R/W
ABACK0_0
R/W
RXPR1_0
R/W
RXPR0_0
R/W
RFPR1_0
R/W
RFPR0_0
R/W
MBIMR1_0
R/W
MBIMR0_0
R/W
UMSR1_0
R/W
UMSR0_0
R/W
Access Size (Bits)
16
16
16
16
16
16
16
16
Rev.3.00 Mar. 12, 2008 Page 451 of 948
REJ09B0177-0300