SH7059 Datasheet, PDF (519/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
Register Name Address
Bit
Bit Name Description
MBx[0], MBx[1]* H'100 + N • 32 1, 0 EXTID [17:16] Extended ID
MBx[2], MBx[3]* H'102 + N • 32 15 to 0 EXTID [15:0] Set the ID (extended ID) of data frames and remote frames.
MBx[4], MBx[5]* H'104 + N • 32 15
CCM
CAN-ID Compare Match
When this bit is set, message reception in the corresponding
mailbox can generate two triggers.
If TCR9 is set to 1, TCR14 is cleared to freeze ICR0. If TCR10 is
set to 1, TCNTR (timer counter register) is automatically cleared
and the LOSR (local offset register) value is set.
Important: This function is not supported by this LSI.
Thus the write value should be 0.
Values read out in the initial state are not guaranteed.
14
TTE
Time Trigger Enable
When this bit is set, a mailbox in which TXPR has been already
set transmits a message at a time set in the Tx trigger time field.
Important: If this bit is set, a failure occurs during message
transmission. Therefore setting prohibited.
The write value should be 0. Values read out in the initial state
are not guaranteed.
13
NMC
New Message Control
When this bit is cleared, a mailbox in which RXPR/RFPR has
been already set does not store the new message but retains the
previous one and sets the UMSR corresponding bit.
When this bit is set, a mailbox in which RXPR/RFPR has been
already set stores the new message and sets the UMSR
corresponding bit.
If a message is received in a mailbox in overwrite mode (NMC =
1), the host CPU must perform an additional check at the end of
the data reading from the mailbox in order to guarantee that the
mailbox data have not been corrupted during such operation by
another receive message. The additional check, to be performed
at the end of the mailbox access, consists in verifying that the
associated bit of UMSR has not been set and so no overwrite has
occurred; in case such bit is set data have been corrupted and so
the message must be discarded.
12
ATX
Automatic Transmission of Data Frame
When this bit is set to 1 and a remote frame is received in the
mailbox, a data frame is automatically transmitted from the same
mailbox using the current contents of the message data. The
scheduling of transmission is controlled by the CAN ID. In order
to use this function, the MBC[2:0] bits should be set to 001. When
transmission is performed by this function, the DLC (data length
code) to be used is the one that has been received.
Important: Note that, when this function is used, the RTR bit is
not set even if a remote frame is received. When a remote frame
is received, the host CPU will be notified by RFPR or IRR2
(remote frame request interrupt), however, as the HCAN needs to
transmit the current message as a data frame, the RTR bit
remains 0.
Rev.3.00 Mar. 12, 2008 Page 429 of 948
REJ09B0177-0300