SH7059 Datasheet, PDF (16/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H)
SH7058S/SH7059
10.3.2 DMA Transfer Requests
179 - 182
On-Chip Peripheral Module Request Mode: In this mode
a transfer is performed at the transfer request signal
(interrupt request signal) of an on-chip peripheral module.
As indicated in table 10.2, there are 26 transfer request
signals: 12 from the advanced timer unit (ATU-II), which
are compare match or input capture interrupts; the receive
data full interrupts (RXI) and transmit data empty interrupts
(TXI) of the five serial communication interfaces (SCI); the
receive interrupt of HCAN0; and the A/D conversion end
interrupts (ADI) of the three A/D converters. When DMA
transfers are enabled (DE = 1, DME = 1, TE = 0, NMIF = 0,
AE = 0), a transfer is performed upon the input of a transfer
request signal.
10.3.2 DMA Transfer Requests
Description amended
On-Chip Peripheral Module Request Mode: In this mode
a transfer is performed at the transfer request signal
(interrupt request signal) of an on-chip peripheral module.
As indicated in table 10.2, there are 26 transfer request
signals: 12 from the advanced timer unit (ATU-II), which
are compare match or input capture interrupts; the receive
data full interrupts (RXI) and transmit data empty interrupts
(TXI) of the five serial communication interfaces (SCI); the
receive interrupt of HCAN0; and the A/D conversion end
interrupts (ADI) of the three A/D converters; the receiver
data full interrupts (SSRXI), transmit data empty or transmit
end interrupts (SSTSI) from two synchronous serial
communication unit (SSU). When DMA transfers are
enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a
transfer is performed upon the input of a transfer request
signal.
When the transfer request is set to RXI (transfer request
because the SCI’s receive data register is full), the transfer
source must be the SCI’s receive data register (RDR).
When the transfer request is set to TXI (transfer request
because the SCI’s transmit data register is empty), the
transfer destination must be the SCI’s transmit data
register (TDR). If the transfer request is set to the A/D
converter, the data transfer source must be the A/D
converter register; if set to HCAN0, the transfer source
must be HCAN0 message data.
When the transfer request is set to RXI (transfer request
because the SCI's receive data register is full), the transfer
source must be the SCI's receive data register (RDR).
When the transfer request is set to TXI (transfer request
because the SCI's transmit data register is empty), the
transfer destination must be the SCI's transmit data register
(TDR). If the transfer request is set to the A/D converter,
the data transfer source must be the A/D converter
register; if set to HCAN0, the transfer source must be
HCAN0 message data. If the transfer request by the
receive data full of the SSU (SSRXI) is selected, the
transfer destination must be the SS receive data register
(SSRDR) of the SSU. If the transmit data empty or transmit
end of the SSU (SSTSI) is selected, the transfer
destination must be the SS transmit data register (SSTDR)
of the SSU.
Rev.3.00 Mar. 12, 2008 Page xvi of xc
REJ09B0177-0300