SH7059 Datasheet, PDF (600/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

18. A/D Converter
ADST
ADF
Set^*1
Continuous A/D conversion
Clear^*1
Clear^*1
State of channel 0
(AN0)
State of channel 1
(AN1)
State of channel 2
(AN2)
State of channel 3
(AN3)
Idle A/D
conver-
sion (1)
Idle
A/D
conver-
sion (2)
Idle
A/D
conver-
sion (3)
Idle
Idle
Idle
Idle
A/D
Idle
conver-
sion (7)
A/D
Idle
conver-
sion (8)
A/D
Idle
conver-
sion (9)
State of channel 4
(AN4)
Idle
State of channel 5
(AN5)
Idle
State of channel 6
(AN6)
Idle
State of channel 7
(AN7)
Idle
A/D
Idle
conver-
sion (4)
A/D
Idle
conver-
sion (5)
A/D
Idle
conver-
sion (6)
A/D
conver-
sion (10)
Idle
*2
A/D
Idle
conver-
sion (11)
ADDR0
A/D conversion result (1)
A/D conversion result (7)
ADDR1
A/D conversion result (2)
A/D conversion result (8)
ADDR2
ADDR3
A/D conversion result (3)
A/D conversion result (9)
ADDR4
A/D conversion result (4)
A/D conversion result (10)
ADDR5
A/D conversion result (5)
ADDR6
A/D conversion result (6)
ADDR7
Notes: 1. Vertical arrows ( ) indicate instructions executed by software.
2. Data currently being converted is ignored.
Figure 18.5 Example of A/D Converter Operation (Scan Mode (Continuous Scan), Channels AN0 to AN2 and AN4
to AN6 Selected)
18.4.3 Analog Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit in A/D0, A/D1, and A/D2. The A/D converter samples the
analog input at time t_D (A/D conversion start delay time) after the ADST bit is set to 1, then starts conversion. Figure 18.6
shows the A/D conversion timing.
The A/D conversion time (t_CONV) includes t_D and the analog input sampling time (t_SPL). The length of t_D is not fixed, since it
includes the time required for synchronization of the A/D conversion operation. The total conversion time therefore varies
within the ranges shown in table 18.4.
Rev.3.00 Mar. 12, 2008 Page 510 of 948
REJ09B0177-0300