SH7059 Datasheet, PDF (224/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Direct Memory Access Controller (DMAC)
10.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)
Bit:
31
30
29
28
27
—
—
—
DI
—
Initial value:
0
0
0
0
0
R/W:
R
R
R
R/W*²
R
Bit:
23
22
21
20
19
—
—
—
RS4
RS3
Initial value:
0
0
0
0
0
R/W:
R
R
R
R/W
R/W
Bit:
15
—
Initial value:
0
R/W:
R
14
13
12
11
—
SM1
SM0
—
0
0
0
0
R
R/W
R/W
R
26
25
24
—
—
RO
0
0
0
R
R
R/W*²
18
17
16
RS2
RS1
RS0
0
R/W
0
R/W*¹
0
R/W
10
9
8
—
DM1
DM0
0
0
0
R
R/W
R/W
Bit:
7
6
5
4
3
—
—
TS1
TS0
TM
Initial value:
0
0
0
0
0
R/W:
R
R
R/W
R/W
R/W
Notes: 1. TE bit: Allows only a 0 write after reading 1.
2. The DI and RO bits may be absent, depending on the channel.
2
1
0
IE
TE
DE
0
0
0
R/W
R/(W)*¹
R/W
DMA channel control registers 0–3 (CHCR0–CHCR3) are 32-bit readable/writable registers that designate the operation
and transmission of each channel. CHCR register bits are initialized to H'00000000 by a power-on reset and in standby
mode.
• Bits 31–29, 27–25, 23–21, 15, 14, 11, 10, 7, 6—Reserved: These bits are always read as 0. The write value should
always be 0.
• Bit 28—Direct/Indirect Select (DI): Specifies either direct address mode operation or indirect address mode operation
for the channel 3 source address. This bit is valid only in CHCR3. This bit is always read as 0 in CHCR0–CHCR2, and
the write value should always be 0.
Bit 28: DI
0
1
Description
Direct access mode operation for channel 3
Indirect access mode operation for channel 3
(Initial value)
• Bit 24—Source Address Reload (RO): Selects whether to reload the source address initial value during channel 2
transfer. This bit is valid only for channel 2. This bit is always read as 0 in CHCR0, CHCR1, and CHCR3, and the
write value should always be 0.
Bit 24: RO
0
1
Description
Does not reload source address
Reloads source address
(Initial value)
Rev.3.00 Mar. 12, 2008 Page 134 of 948
REJ09B0177-0300