SH7059 Datasheet, PDF (293/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
• Bit 7—Interval Interrupt Flag 2B (IIF2B): Status flag that indicates the generation of an interval interrupt.
Bit 7: IIF2B
0
1
Description
[Clearing condition]
When IIF2B is read while set to 1, then 0 is written to IIF2B
[Setting condition]
When interval interrupt selected by ITVRR2B is generated
(Initial value)
• Bit 6—Interval Interrupt Flag 2A (IIF2A): Status flag that indicates the generation of an interval interrupt.
Bit 6: IIF2A
0
1
Description
[Clearing condition]
When IIF2A is read while set to 1, then 0 is written to IIF2A
[Setting condition]
When interval interrupt selected by ITVRR2A is generated
(Initial value)
• Bit 5—Interval Interrupt Flag 1 (IIF1): Status flag that indicates the generation of an interval interrupt.
Bit 5: IIF1
0
1
Description
[Clearing condition]
When IIF1 is read while set to 1, then 0 is written to IIF1
[Setting condition]
When interval interrupt selected by ITVRR1 is generated
(Initial value)
• Bit 4—Overflow Flag 0 (OVF0): Status flag that indicates TCNT0 overflow.
Bit 4: OVF0
0
1
Description
[Clearing condition]
When OVF0 is read while set to 1, then 0 is written to OVF0
[Setting condition]
When the TCNT0 value overflows (from H'FFFFFFFF to H'00000000)
(Initial value)
• Bit 3—Input Capture Flag 0D (ICF0D): Status flag that indicates ICR0D input capture.
Bit 3: ICF0D
0
1
Description
[Clearing condition]
When ICF0D is read while set to 1, then 0 is written to ICF0D
(Initial value)
[Setting condition]
When the TCNT0 value is transferred to the input capture register by an input capture signal.
Also set by input capture with a channel 10 compare match as the trigger
• Bit 2—Input Capture Flag 0C (ICF0C): Status flag that indicates ICR0C input capture.
Bit 2: ICF0C
0
1
Description
[Clearing condition]
When ICF0C is read while set to 1, then 0 is written to ICF0C
(Initial value)
[Setting condition]
When the TCNT0 value is transferred to the input capture register by an input capture signal
Rev.3.00 Mar. 12, 2008 Page 203 of 948
REJ09B0177-0300