SH7059 Datasheet, PDF (355/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
General Registers 1A to 1H and 2A to 2H (GR1A to GR1H, GR2A to GR2H)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
These GR registers are 16-bit readable/writable registers with both input capture and output compare functions. Function
switching is performed by means of the timer I/O control registers (TIOR).
When a general register is used for input capture, it stores the TCNT1A or TCNT2A value on detection of an input capture
signal from an external source. The corresponding IMF bit in TSR is set to 1 at this time. The input capture signal edge to
be detected is specified by the corresponding TIOR.
When a general register is used for output compare, the GR value and free-running counter (TCNT1A, TCNT2A) value
are constantly compared, and when both values match, the IMF bit in the timer status register (TSR) is set to 1. If
connection of channels 1 and 2 and channel 8 is specified in the timer connection register (TCNR), the corresponding
channel 8 down-counter (DCNT) is started. Compare-match output is specified by the corresponding TIOR.
The GR registers can only be accessed by a word read or write.
The GR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby
mode.
General Registers 3A to 3D, 4A to 4D, 5A to 5D, 11A and 11B
(GR3A to GR3D, GR4A to GR4D, GR5A to GR5D, GR11A and GR11B)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
These GR registers are 16-bit readable/writable registers with both input capture and output compare functions. Function
switching is performed by means of the timer I/O control registers (TIOR).
When a general register is used for input capture, it stores the corresponding TCNT value on detection of an input capture
signal from an external source. The corresponding IMF bit in TSR is set to 1 at this time. The input capture signal edge to
be detected is specified by the corresponding TIOR. GR3A to GR3D can also be used for input capture with a channel 9
compare-match as the trigger. In this case, the corresponding IMF bit in TSR is not set.
When a general register is used for output compare, the GR value and free-running counter (TCNT) value are constantly
compared, and when both values match, the IMF bit in the timer status register (TSR) is set to 1. Compare-match output is
specified by the corresponding TIOR.
GRIIA and GR11B compare-match signals are transmitted to the advanced pulse controller (APC). For details, see section
12, Advanced Pulse Controller (APC).
The GR registers can only be accessed by a word read or write.
The GR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby
mode.
Rev.3.00 Mar. 12, 2008 Page 265 of 948
REJ09B0177-0300