SH7059 Datasheet, PDF (182/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Interrupt Controller (INTC)
Program
execution state
Interrupt?
No
Yes
NMI?
No
Yes
User break?
No
Yes
H-UDI
No
interrupt?
IRQOUT = low level*¹
Save SR to stack
Save PC to stack
Copy accept-interrupt
level to I3 to I0
IRQOUT = high level*²
Yes
Yes
Level 15 No
interrupt?
Yes
I3 to I0 ≤
level 14?
No _Yes
Level 14
interrupt?
Yes
I3 to I0 ≤
level 13?
No
Level 1 ^No
interrupt?
Yes
No Yes
I3 to I0 =
level 0?
Read exception
No
vector table
Branch to exception
service routine
Notes: I3 to I0: Interrupt mask bits of status register
1. As IRQOUT is synchronized with a peripheral clock Pφ, it may be output later than a
CPU interrupt request.
2. When the accepted interrupt is sensed by edge, the IRQOUT pin becomes high level at the
point when the CPU starts interrupt exception processing instead of instruction execution
(before SR is saved to the stack).
If the interrupt controller has accepted another interrupt with a higher priority and has
output an interrupt request to the CPU, the IRQOUT pin will remain low.
Figure 7.2 Interrupt Sequence Flowchart
Rev.3.00 Mar. 12, 2008 Page 92 of 948
REJ09B0177-0300