SH7059 Datasheet, PDF (467/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Serial Communication Interface (SCI)
e. Marking: output of 1-bits continues until the start bit of the next transmit data.
3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads new data from TDR into TSR,
outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit to 1 in
SSR, outputs the stop bit, then continues output of 1-bits (marking). If the transmit-end interrupt enable bit (TEIE) in
SCR is set to 1, a transmit-end interrupt (TEI) is requested.
Figure 15.6 shows an example of SCI transmit operation in asynchronous mode.
1
Serial
data
Start
bit
0 D0
Data
Parity Stop Start
bit bit bit
D1 D7 0/1 1 0 D0
Data
Parity Stop
bit bit
1
D1 D7 0/1 1 ^Idling
(marking)
TDRE
TEND
TXI
interrupt
request
TXI interrupt
handler writes
data in TDR
and clears
TDRE to 0
TXI interrupt
request
1 frame
TEI interrupt request
Figure 15.6 SCI Transmit Operation in Asynchronous Mode
(Example: 8-Bit Data with Parity and One Stop Bit)
Receiving Serial Data (Asynchronous Mode): Figures 15.7 and 15.8 show a sample flowchart for receiving serial data.
The procedure is as follows (the steps correspond to the numbers in the flowchart).
Rev.3.00 Mar. 12, 2008 Page 377 of 948
REJ09B0177-0300