SH7059 Datasheet, PDF (564/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
17.7.2 HCAN Settings
• Reset Sequence
The following sequence is an example to set the HCAN after a software or hardware reset. After a reset, all the registers
are initialized, therefore, the HCAN needs to be set before joining the CAN bus activity. Please read the notes carefully.
Reset Sequence
Configuration Mode
Power-on/software reset^*1
Clear MCR[0]
Setting of the endian for use
in transmission
Clear all mailboxes^*2
(MSG-control, data, timestamp,
LAFM, Txtrigger)
GSR3 = 0?
No
Yes
Clear IRR[0]
Clear required IMR bits
HCAN-II is in normal mode
Set TXPR to start transmission
or stay idle to receive
Set LAFM
Mailbox setting
(STD-ID, EXT-ID, DLC, RTR,
IDE, MBC, MBIMR, ATX, NMC,
LAFM, message data)
Set bit configuration register
(BCR)
Normal Mode
Detect 11 recessive bits and
join the CAN bus activity
Receive^*3
Transmit^*3
Notes: 1.
2.
3.
A software reset can be performed at any time by setting MCR [0] = 1.
Mailboxes are comprised of RAMs, therefore, initialize all the mailboxes first
even if some of them are not used.
If TXPR is not set, the HCAN-II starts the message reception. If TXPR is set,
the HCAN-II starts transmission of the message and is arbitrated by the CAN bus.
If an arbitration loss occurs, reception starts.
Figure 17.7 Reset Sequence
Rev.3.00 Mar. 12, 2008 Page 474 of 948
REJ09B0177-0300