SH7059 Datasheet, PDF (741/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

24. ROM (SH7058S)
Table 24.4 (2) Parameter Configuration
Name
Abbreviation
R/W
Initial Value Address
Download pass/fail result
DPFR
R/W
Undefined
On-chip RAM*
Flash pass/fail result
FPFR
R/W
Undefined
R0 of CPU
Flash multipurpose address
area
FMPAR
R/W
Undefined
R5 of CPU
Flash multipurpose data
destination area
FMPDR
R/W
Undefined
R4 of CPU
Flash erase block select
FEBS
R/W
Undefined
R4 of CPU
Flash program and erase
frequency control
FPEFEQ
R/W
Undefined
R4 of CPU
Flash user branch address set FUBRA
parameter
R/W
Undefined
R5 of CPU
Note: * One byte of the start address in the on-chip RAM area specified by FTDAR is valid.
Access
Size
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
Table 24.5 Register/Parameter and Target Mode
Download
Initiali-
zation
Program-
ming
Erasure
Read
RAM
Emulation
Programming/ FCCS
O
—
—
—
—
—
erasing
FPCS
O
—
—
—
—
—
interface
registers
PECS
O
FKEY
O
FMATS
—
—
—
—
—
—
—
O
O
—
—
—
O*¹
O*¹
O*²
—
FTDAR
O
—
—
—
—
—
Programming/ DPFR
O
—
—
—
—
—
erasing
FPFR
O
O
O
O
—
—
interface
parameters
FPEFEQ —
FUBRA
—
O
—
—
—
—
O
—
—
—
—
FMPAR
—
—
O
—
—
—
FMPDR
—
—
O
—
—
—
FEBS
—
—
—
O
—
—
RAM
emulation
RAMER
—
—
—
—
—
O
Notes: 1. The setting is required when programming or erasing user MAT in user boot mode.
2. The setting may be required according to the combination of initiation mode and read target MAT.
Rev.3.00 Mar. 12, 2008 Page 651 of 948
REJ09B0177-0300