SH7059 Datasheet, PDF (557/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
17.6.4 Timer Mode Register_n (TMR_n) (n = 0, 1)
The timer mode register (TMR) is a 16-bit readable/writable register that specifies the value to be used for the timer
functions.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR3 TMR2 TMR1
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ R/W R/W R/W ⎯
Bit
Bit Name
15 to 4 —
3
TMR3
2
TMR2
1
TMR1
0
—
Initial Value R/W
0
—
0
R/W
0
R/W
0
R/W
0
—
Description
Reserved
Writing 0 to this bit is ignored. The read value is not guaranteed.
Timestamp Value
Specifies whether the timestamp for transmission and reception contains the
timer value (TCNTR) or the value of Cycle_Counter + TCNTR[15:4]. This
function is very useful for time triggered transmission.
0: TCNTR[15:0] is used for the timestamp
1: Cycle_Counter + TCNTR[15:4] is used for the timestamp
TCMR2 Control
Specifies whether the timer compare match 2 is compared with the timer
value (TCNTR) or with Cycle_Counter + TCNTR[15:4].
0: TCNTR[15:0] is used for a compare match
1: Cycle_Counter + TCNTR[15:4] is used for a compare match
TCMR1 Control
Specifies whether the timer compare match 1 is compared with the timer
value (TCNTR) or with Cycle_Counter + TCNTR[15:4].
0: TCNTR[15:0] is used for a compare match
1: Cycle_Counter + TCNTR[15:4] is used for a compare match
Reserved
Writing 0 to this bit is ignored. The read value is not guaranteed.
17.6.5 Timer Drift Correction Register n (TDCRn) (n = 0, 1)
The timer drift correction register (TDCR) is a 16-bit readable/writable register. The purpose of this register is to adjust
the drift of the timer caused by a different clock running at other CAN nodes on the same system. When TCNTR reaches
to the cycle specified by this register, the timer value is incremented by 2 or 0 (i.e. retains the same value). This register
does not point at a specific time nor a specific cycle. This means, if TCNTR/2 > TDCR, the drift correction will be
performed more than twice (unless TCMR0 is used to clear TCNTR before it reaches the second cycle). When TDCR is
set to H'0000, the drift correction will not be performed at all.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDCR[15:0]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev.3.00 Mar. 12, 2008 Page 467 of 948
REJ09B0177-0300