SH7059 Datasheet, PDF (298/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
• Bit 8—Overflow Flag 2A (OVF2A): Status flag that indicates TCNT2A overflow.
Bit 8: OVF2A
0
1
Description
[Clearing condition]
When OVF2A is read while set to 1, then 0 is written to OVF2A
[Setting condition]
When the TCNT2A value overflows (from H'FFFF to H'0000)
(Initial value)
• Bit 7—Input Capture/Compare-Match Flag 2H (IMF2H): Status flag that indicates GR2H input capture or compare-
match.
Bit 7: IMF2H
0
1
Description
[Clearing condition]
When IMF2H is read while set to 1, then 0 is written to IMF2H
(Initial value)
[Setting conditions]
• When the TCNT2A value is transferred to GR2H by an input capture signal while GR2H
is functioning as an input capture register
• When TCNT2A = GR2H while GR2H is functioning as an output compare register
• Bit 6—Input Capture/Compare-Match Flag 2G (IMF2G): Status flag that indicates GR2G input capture or compare-
match.
Bit 6: IMF2G
0
1
Description
[Clearing condition]
When IMF2G is read while set to 1, then 0 is written to IMF2G
(Initial value)
[Setting conditions]
• When the TCNT2A value is transferred to GR2G by an input capture signal while GR2G
is functioning as an input capture register
• When TCNT2A = GR2G while GR2G is functioning as an output compare register
• Bit 5—Input Capture/Compare-Match Flag 2F (IMF2F): Status flag that indicates GR2F input capture or compare-
match.
Bit 5: IMF2F
0
1
Description
[Clearing condition]
When IMF2F is read while set to 1, then 0 is written to IMF2F
(Initial value)
[Setting conditions]
• When the TCNT2A value is transferred to GR2F by an input capture signal while GR2F is
functioning as an input capture register
• When TCNT2A = GR2F while GR2F is functioning as an output compare register
Rev.3.00 Mar. 12, 2008 Page 208 of 948
REJ09B0177-0300