SH7059 Datasheet, PDF (139/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
Power-On Reset State: The CPU resets in the reset state. When the HSTBY pin is driven high and the RES pin level goes
low, the power-on reset state is entered.
Exception Processing State: The exception processing state is a transient state that occurs when exception processing
sources such as resets or interrupts alter the CPU's processing state flow.
For a reset, the initial values of the program counter (PC) (execution start address) and stack pointer (SP) are fetched from
the exception processing vector table and stored; the CPU then branches to the execution start address and execution of the
program begins.
For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status register (SR) are saved to the
stack area. The exception service routine start address is fetched from the exception processing vector table; the CPU then
branches to that address and the program starts executing, thereby entering the program execution state.
Program Execution State: In the program execution state, the CPU sequentially executes the program.
Power-Down State: In the power-down state, the CPU operation halts and power consumption declines. The SLEEP
instruction places the CPU in the sleep mode or the software standby mode. If the HSTBY pin is driven low when the RES
pin is low, the CPU will enter the hardware standby mode.
Bus Release State: In the bus release state, the CPU releases access rights to the bus to the device that has requested them.
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