SH7059 Datasheet, PDF (63/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H)
25.1.1 Power-Down States
Table 25.1 Power-Down State Conditions
944
State
Mode
On-Chip
Entering
CPU
Peripheral
Procedure Clock CPU Registers Modules RAM Pins
Canceling
Procedure
Hardware Low-level Halted Halted Undefined Halted
standby input at
HSTBY pin
Held*² Initialized High-level input
at HSTBY pin,
executing
power-on reset
Software
standby
Execute
Halted Halted Held
SLEEP
instruction
with SSBY
bit set to 1 in
SBYCR
Halted*¹
Held
Held or
high
impe-
dance*³
NMI
interrupt
Power-on
reset
Sleep
Execute
Runs
SLEEP
instruction
with SSBY
bit cleared to
0 in SBYCR
Halted Held
Runs
Held Held
Interrupt
DMA
address
error
Power-on
reset
Manual
reset
Notes:
1. Some bits within on-chip peripheral module registers are
initialized in software standby mode, and some are not.
Refer to the register descriptions for each peripheral
module.
2. Clear the RAME bit in SYSCR1 to 0 in advance when
changing the state from the program execution state in
hardware standby mode.
3. The state of the I/O ports in standby mode is set by the
port high impedance bit (HIZ) in SBYCR. See section
25.2.1, Standby Control Register (SBYCR).
25.1.2 Pin Configuration
Table 25.2 Pin Configuration
945
25.1.3 Related Registers
Table 25.3 Related Registers
945
Abbreviation*¹
Notes: 1. Register access with an internal clock
multiplication ratio of 4 requires four internal clock (φ)
cycles for SBYCR, and four or five internal clock (φ) cycles
for SYSCR1 and SYSCR2.
SH7058S/SH7059
27.1.1 Power-Down States
Table 27.1 Power-Down State Conditions
Description of CPU Registers deleded and table amended
Mode
Hardware
standby
Software
standby
Entering Procedure
Clock
Low-level input at HSTBY Halted
pin
(Power
supply
stopped)
Execute SLEEP instruction Halted
with SSBY
bit set to 1 in SBYCR
(Power
supply
stopped)
CPU
Halted
(Power
supply
stopped)
Halted
(Power
supply
stopped)
State
On-Chip
Peripheral
Modules
RAM
Halted
Held*¹
(Power supply
stopped)
Halted*¹
Held
(Power supply
stopped)
Pins
Initialized
Canceling
Procedure
High-level input at
HSTBY pin,
executing
power-on reset
High
impedance*²
Rising edge of
NMI
Power-on
reset
Sleep
Execute SLEEP instruction Runs
with SSBY
bit cleared to 0 in SBYCR
Halted and Runs
held in
registers
Runs
Runs
Interrupt
DMA address
error
Power-on
reset
Manual reset
Note *1 deleted and notes amended
Notes:
1. Clear the RAME bit in SYSCR1 to 0 in advance when
changing the state from the program execution state in
hardware standby mode.
2. When leaving software standby mode, the inside of this
LSI is initiated in the reset state. The pin function controller
and I/O port-related registers are initialized. For details on
the pin state, see Appendix B, Pin States.
27.1.2 Pin Configuration
Table 27.2 Pin Configuration
Table amended
Description of NMI input pin added
27.1.3 Related Registers
Table 27.3 Related Registers
Table amended
Abbreviation .
Note*¹ deleted
Rev.3.00 Mar. 12, 2008 Page lxiii of xc
REJ09B0177-0300