SH7059 Datasheet, PDF (247/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
Section 11 Advanced Timer Unit-II (ATU-II)
11.1 Overview
This LSI has an on-chip advanced timer unit-II (ATU-II) with one 32-bit timer channel and eleven 16-bit timer channels.
11.1.1 Features
ATU-II features are summarized below.
• Capability to process up to 65 pulse inputs and outputs
• Prescaler
⎯ Input clock to channels 0 and 10 scaled in 1 stage, input clock to channels 1 to 8 and 11 scaled in 2 stages
⎯ 1/1 to 1/32 clock scaling possible in initial stage for channels 0 to 8, 10, and 11
⎯ 1/1, 1/2, 1/4, 1/8, 1/16, or 1/32 scaling possible in second stage for channels 1 to 8 and 11
⎯ External clock TCLKA, TCLKB selection also possible for channels 1 to 5 and 11
⎯ TI10, TI10 multiplication (compensation) selection possible for channels 1 to 5: AGCK, AGCKM
• Channel 0 has four 32-bit input capture lines, allowing the following operations:
⎯ Rising-edge, falling-edge, or both-edge detection selectable
⎯ DMAC can be activated at capture timing
⎯ Channel 10 compare-match signal can be captured as a trigger
⎯ Interval interrupt generation function generates three interval interrupts as selected. CPU interruption or A/D
converter (AD0, 1, 2) activation possible
⎯ Capture interrupt and counter overflow interrupt can be generated
• Channel 1 has one 16-bit output compare register, eight general registers, and one dedicated input capture register. The
output compare register can also be selected for one-shot pulse offset in combination with the channel 8 down-counter.
⎯ General registers (GR1A–H) can be used as input capture or output compare registers
⎯ Waveform output by means of compare-match: Selection of 0 output, 1 output, or toggle output
⎯ Input capture function: Rising-edge, falling-edge, or both-edge detection
⎯ Channel 0 input signal (TI0A) can be captured as trigger
⎯ Provision for forcible cutoff of channel 8 down-counters (DCNT8A–H)
⎯ Compare-match interrupts/capture interrupts and counter overflow interrupts can be generated
• Channel 2 has eight 16-bit output compare registers, eight general registers, and one dedicated input capture register.
The output compare registers can also be selected for one-shot pulse offset in combination with the channel 8 down-
counter.
⎯ General registers (GR2A–H) can be used as input capture or output compare registers
⎯ Waveform output by means of compare-match: Selection of 0 output, 1 output, or toggle output
⎯ Input capture function: Rising-edge, falling-edge, or both-edge detection
⎯ Channel 0 input signal (TI0A) can be captured as trigger
⎯ Provision for forcible cutoff of channel 8 down-counters (DCNT8I–P)
⎯ Compare-match interrupts/capture interrupts and counter overflow interrupts can be generated
• Channels 3 to 5 each have four general registers, allowing the following operations:
⎯ Selection of input capture, output compare, PWM mode
⎯ Waveform output by means of compare-match: Selection of 0 output, 1 output, or toggle output
⎯ Input capture function: Rising-edge, falling-edge, or both-edge detection
Rev.3.00 Mar. 12, 2008 Page 157 of 948
REJ09B0177-0300