SH7059 Datasheet, PDF (442/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Compare Match Timer (CMT)
14.5.3 Contention between CMCNT Byte Write and Incrementation
If an increment occurs during the T2 state of the CMCNT byte write cycle, the counter write has priority, so no increment
of the write data results on the side on which the write was performed. The byte data on the side on which writing was not
performed is also not incremented, so the contents are those before the write.
Figure 14.8 shows the timing when an increment occurs during the T2 state of the CMCNTH write cycle.
CMCNT write cycle
T1
T2
Pφ
Address
Internal
write signal
CMCNT
input clock
CMCNTH
CMCNTH
N
CMCNTL
X
M
CMCNTH write data
X
Figure 14.8 CMCNT Byte Write and Increment Contention
Rev.3.00 Mar. 12, 2008 Page 352 of 948
REJ09B0177-0300