SH7059 Datasheet, PDF (430/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Watchdog Timer (WDT)
Writing to TCNT
15
Address: H'FFFFEC10
H'5A
87
0
Write data
Writing to TCSR
15
Address: H'FFFFEC10
H'A5
87
0
Write data
Figure 13.2 Writing to TCNT and TCSR
Writing to RSTCSR: RSTCSR must be written by a word access to address H'FFFFEC12. It cannot be written by byte
transfer instructions.
Procedures for writing 0 to WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in
figure 13.3.
To write 0 to the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte. This clears the
WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the RSTE and RSTS bits, the upper byte must be
H'5A and the lower byte must be the write data. The values of bits 6 and 5 of the lower byte are transferred to the RSTE
and RSTS bits, respectively. The WOVF bit is not affected.
Writing 0 to the WOVF bit
15
87
0
Address: H'FFFFEC12
H'A5
H'00
Writing to the RSTE and RSTS bits
15
Address: H'FFFFEC12
H'5A
87
0
Write data
Figure 13.3 Writing to RSTCSR
Reading from TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like other registers. Use byte transfer
instructions. The read addresses are H'FFFFEC10 for TCSR, H'FFFFEC11 for TCNT, and H'FFFFEC13 for RSTCSR.
13.3 Operation
13.3.1 Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/IT and TME bits in TCSR to 1. Software must prevent TCNT overflow
by rewriting the TCNT value (normally by writing H'00) before overflow occurs. No TCNT overflows will occur while
the system is operating normally, but if TCNT fails to be rewritten and overflows occur due to a system crash or the like, a
WDTOVF signal is output externally (figure 13.4). The WDTOVF signal can be used to reset the system. The WDTOVF
signal is output for 128 φ clock cycles.
If the RSTE bit in RSTCSR is set to 1, a signal to reset the chip will be generated internally simultaneous with the
WDTOVF signal when TCNT overflows. Either a power-on reset or a manual reset can be selected by the RSTS bit in
RSTCSR. The internal reset signal is output for 512 φ clock cycles.
Rev.3.00 Mar. 12, 2008 Page 340 of 948
REJ09B0177-0300