SH7059 Datasheet, PDF (220/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Direct Memory Access Controller (DMAC)
10.1.2 Block Diagram
Figure 10.1 is a block diagram of the DMAC.
On-chip ROM
On-chip RAM
On-chip
peripheral
module
HCAN0
ATU-II
SCI0–SCI4
A/D converter 0–2
SSU0*, SSU1*
DEIn
DMAC module
Circuit
control
SARn
Register
control
Activation
control
DARn
DMATCRn
CHCRn
Request
priority
control
DMAOR
External
ROM
External
RAM
External I/O
(memory
mapped)
Bus interface
Bus state
controller
Legend:
SARn:
DMA source address register
DARn:
DMA destination address register
DMATCRn: DMA transfer count register
CHCRn: DMA channel control register
DMAOR: DMA operation register
Notes: n = 0 to 3
* SSU: Synchronous Serial Communication Unit
Figure 10.1 DMAC Block Diagram
10.1.3 Register Configuration
Table 10.1 summarizes the DMAC registers. The DMAC has a total of 17 registers. Each channel has four registers, and
one overall DMAC control register is shared by all channels.
Rev.3.00 Mar. 12, 2008 Page 130 of 948
REJ09B0177-0300