SH7059 Datasheet, PDF (368/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
• Bit 2—Compare-Match Flag 10B (CMF10B): Status flag that indicates OCR10B compare-match.
Bit 2: CMF10B
0
1
Description
[Clearing condition]
When CMF10B is read while set to 1, then 0 is written to CMF10B
[Setting condition]
When TCNT10B is incremented while TCNT10B = OCR10B
(Initial value)
• Bit 1—Input Capture Flag 10A (ICF10A): Status flag that indicates ICR10A input capture.
Bit 1: ICF10A
0
1
Description
[Clearing condition]
When ICR10A is read while set to 1, then 0 is written to ICR10A
(Initial value)
[Setting condition]
When the TCNT10A value is transferred to ICR10A by an input capture signal
• Bit 0—Compare-Match Flag 10A (CMF10A): Status flag that indicates OCR10A compare-match.
Bit 0: CMF10A
0
1
Description
[Clearing condition]
When CMF10A is read while set to 1, then 0 is written to CMF10A
[Setting condition]
When TCNT10A = OCR10A
(Initial value)
Timer Interrupt Enable Register 10 (TIER10): TIER10 is a 16-bit readable/writable register that controls
enabling/disabling of channel 10 input capture and compare-match interrupt requests.
TIER10 is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode.
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
IREG CME10G CME10B ICE10A CME10A
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R/W
R/W
R/W
R/W
R/W
• Bits 15 to 5—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 4—Interrupt Enable Edge G (IREG): Specifies TSR10 CMF10G interrupt request timing.
Bit 4: IREG
0
1
Description
Interrupt is requested when CMF10G becomes 1
(Initial value)
Interrupt is requested by next external input (TI10) (AGCK) after CMF10G becomes 1
Rev.3.00 Mar. 12, 2008 Page 278 of 948
REJ09B0177-0300