SH7059 Datasheet, PDF (370/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
11.3 Operation
11.3.1 Overview
The ATU-II has twelve timers of eight kinds in channels 0 to 11. It also has a built-in prescaler that generates input clocks,
and it is possible to generate or select internal clocks of the required frequency independently of circuitry outside the
ATU-II.
The operation of each channel and the prescaler is outlined below.
Channel 0: Channel 0 has a 32-bit free-running counter (TCNT0) and four 32-bit input capture registers (ICR0A to
ICR0D). TCNT0 is an up-counter that performs free-running operation. An interrupt request can be generated on counter
overflow. The four input capture registers (ICR0A to ICR0D) capture the free-running counter (TCNT0) value by means
of input from the corresponding external signal input pin (TI0A to TI0D). For capture by means of input from an external
signal input pin, rising edge, falling edge, or both edges can be selected in the timer I/O control register (TIOR0). In the
case of input capture register 0D (ICR0D) only, capture can be performed by means of a compare-match between free-
running counter 10B (TCNT10B) and compare-match register 10B (OCR10B), by making a setting in timer control
register 10 (TCR10). In this case, capture is performed even if an input capture disable setting has been made for TIOR0.
In each case, the DMAC can be activated or an interrupt requested when capture occurs.
Channel 0 also has three interval interrupt request registers (ITVRR1, ITVRR2A, and ITVRR2B). A/D converter (AD0 to
AD2) activation can be selected by setting 1 in ITVA6 to ITVA13 in ITVRR, and an interrupt request to the CPU by
setting 1 in ITVE6 to ITVE13. These operations are performed when the corresponding bit of bits 6 to 13 in TCNT0
changes to 1, enabling use as an interval timer function.
Channel 1: Channel 1 has two 16-bit free-running counters (TCNT1A and TCNT1B), eight 16-bit general registers
(GR1A to GR1H), and a 16-bit output compare register (OCR1).
TCNT1A and TCNT1B are up-counters that perform free-running operation. When the clock generated in channel 10
(described below) is selected, these counters can be cleared at the count specified in channel 10. Each counter can generate
an interrupt request when it overflows.
The eight general registers (GR1A to GR1H) can be used as input capture or output compare registers using the
corresponding external signal I/O pin (TIO1A to TIO1H). When used for input capture, the free-running counter
(TCNT1A) value is captured by means of input from the corresponding external signal I/O pin (TIO1A to TIO1H). Rising
edge, falling edge, or both edges can be selected for the input capture signal in the timer I/O control registers (TIOR1A to
TIOR1D). When used for output compare, compare-match with the free-running counter (TCNT1A) is performed. For the
output from the external signal I/O pins by compare-match, 0 output, 1 output, or toggle output can be selected in the timer
I/O control registers (TIOR1A to TIOR1D). When used as output compare registers, a compare-match can be used as a
one-shot pulse start/terminate trigger by setting the channel 8 timer connection register (TCNR) and one-shot pulse
terminate register (OTR), and using these in combination with the down-counters (DCNT8A to DCNT8H). Start/terminate
trigger selection is performed by means of the trigger mode register (TRGMDR).
In the case of the output compare register (OCR1), a TCNT1B compare-match can be used as a one-shot pulse start
trigger, in the same way as the general registers, in combination with channel 8 down-counters DCNT8A to DCNT8H. An
interrupt can be requested on the occurrence of the respective input capture or compare-match.
In addition, channel 1 has a 16-bit dedicated input capture register (OSBR1). The channel 0 TI0A input pin can also be
used as the OSBR1 trigger input, enabling use of a twin-capture function.
Channel 2: Channel 2 has two 16-bit free-running counters (TCNT2A and TCNT2B), eight 16-bit general registers
(GR2A to GR2H), and eight 16-bit output compare registers (OCR2A to OCR2H).
Rev.3.00 Mar. 12, 2008 Page 280 of 948
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