SH7059 Datasheet, PDF (544/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
• TXPR0n (n = 0, 1)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXPR0[15:1]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R
Bit
Bit Name Initial Value R/W Description
15 to 1 TXPR0[15:1] 0
R/W*
Request the corresponding mailbox to transmit a CAN frame. Bits 15 to 1
correspond to mailboxes 15 to 1 respectively. When multiple bits are set, the
order of the transmissions is determined by MCR2 (CAN-ID or mailbox
number).
0: Corresponding mailbox is in transmit message idle state
Clearing condition: Completion of message transmission or message
transmission wait abortion (automatically cleared)
1: Transmission request made for corresponding mailbox
0
⎯
0
R
Reserved
This bit is always 0 as this is a receive-only mailbox. Writing 1 to this bit is
ignored. The read value is not guaranteed.
Note: * Only 1 can be written to set a mailbox for transmission.
17.5.2 Transmit Wait Cancel Register n (TXCR1n, TXCR0n) (n = 0, 1)
TXCR1 and TXCR0 are 16-bit readable/conditionally-writable registers. TXCR1 controls mailbox 31 to mailbox 16, and
TXCR0 controls mailbox 15 to mailbox 1. This register is used by the host CPU to request the transmission wait messages
in TXPR to be cancelled. To clear the corresponding bit in TXPR, the host CPU must write 1 to the bit in TXCR. Writing
0 is ignored.
When transmission cancellation has succeeded, the CAN controller clears the corresponding TXPR and TXCR bits, and
sets the corresponding ABACK bit. However, once a mailbox has started a transmission, it cannot be cancelled by this bit.
In such a case, if the transmission finishes in success, the CAN controller clears the corresponding TXPR and TXCR bits,
and sets the corresponding TXACK bit, however, if the transmission fails due to a bus arbitration loss or an error on the
bus, the CAN controller clears the corresponding TXPR and TXCR bits, and sets the corresponding ABACK bit. If an
attempt is made by the host CPU to cancel a mailbox transmission that is not transmit-waiting, it shall have no effect, and
will be automatically cleared when an internal arbitration for transmission runs.
Important: For details on the method of canceling a transmit wait, see section 17.7, Operation.
Important: If mailbox 31 is used as a transmit buffer, there is a usage limitation. For details, see section 17.8, Usage
Notes.
• TXCR1n (n = 0, 1)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCR1[15:0]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Rev.3.00 Mar. 12, 2008 Page 454 of 948
REJ09B0177-0300