SH7059 Datasheet, PDF (943/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

29.3.12 H-UDI Timing
Table 29.17 shows H-UDI timing.
Table 29.17 H-UDI Timing
Conditions: V_CC = PLLV_CC = 3.3 V ±0.3 V, PV_CC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V,
PV_CC2 = 5.0 V ±0.5 V, AV_CC = 5.0 V ±0.5 V, AV_ref = 4.5 V to AV_CC,
V_SS = PLLV_SS = AV_SS = 0 V, T_a = –40°C to 125°C.
When PV_CC1 = 3.3 V ±0.3 V, V_CC = PV_CC1.
When writing or erasing on-chip flash memory, T_a = –40°C to 85°C.
Item
Symbol
Min
Max
TCK clock cycle
TCK clock high-level width
TCK clock low-level width
TRST pulse width
TRST setup time
TMS setup time
TMS hold time
TDI setup time
TDI hold time
TDO delay time 1
TDO delay time 2
t
2
—
tcyc
t_TCKH
0.4
0.6
t_TCKL
0.4
0.6
t_TRSW
20
—
t_TRSS
30
—
t
30
—
TMSS
t
10
—
TMSH
t_TDIS
30
—
t_TDIH
10
—
t_TDOD1
—
30
t
—
30
TDOD2
29. Electrical Characteristics
Unit
t
tcyc
t_tcyc
t_tcyc
t_cyc
ns
ns
ns
ns
ns
ns
ns
Figures
Figure 29.22
Figure 29.23
Figure 29.24
Figure 29.25
[Operating precautions]
The H-UDI pins constitute a circuit requiring the voltage of V_CC = 3.3 V ±0.3 V. Comply with the input and output
voltages specified in the DC characteristics, for operation.
TCK
t_TCKH
t_TCKL
V_IH
V_IH
V_IL
t_tcyc
V_IH
V_IL
Figure 29.22 H-UDI Clock Timing
TCK
TRST
V_IL
t_TRSS
V_IL
t_TRSS
V_IL
V_IL
t_TRSW
Figure 29.23 H-UDI TRST Timing
Rev.3.00 Mar. 12, 2008 Page 853 of 948
REJ09B0177-0300