SH7059 Datasheet, PDF (192/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. User Break Controller (UBC)
• Bits 3 and 2—Read/Write Select (RW1, RW0): These bits select whether to break on read and/or write cycles.
Bit 3: RW1
0
1
Bit 2: RW0
0
1
0
1
Description
No user break interrupt occurs
Break on read cycles
Break on write cycles
Break on both read and write cycles
(Initial value)
• Bits 1 and 0—Operand Size Select (SZ1, SZ0): These bits select operand size as a break condition.
Bit 1: SZ1
Bit 0: SZ0
Description
0
0
Operand size is not a break condition
(Initial value)
1
Break on byte access
1
0
Break on word access
1
Break on longword access
Note:
When breaking on an instruction fetch, clear the SZ0 bit to 0. All instructions are considered to be word-size
accesses (even when there are instructions in on-chip memory and two instruction fetches are performed
simultaneously in one bus cycle).
Operand size is word for instructions or determined by the operand size specified for the CPU/DMAC data access. It
is not determined by the bus width of the space being accessed.
8.2.4 User Break Control Register (UBCR)
Bit:
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
CKS1
CKS0
UBID
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R/W
R/W
R/W
The user break control register (UBCR) is a 16-bit readable/writable register that (1) enables or disables user break
interrupts and (2) sets the pulse width of the UBCTRG signal output in the event of a break condition match.
UBCR is initialized to H'0000 by a power-on reset, in module standby mode, and in software standby mode.
• Bits 15 to 3—Reserved: These bits are always read as 0. The write value should always be 0.
• Bits 2 and 1—Clock Select 1 and 0 (CKS1, CKS0): These bits specify the pulse width of the UBCTRG signal output
in the event of a condition match.
Rev.3.00 Mar. 12, 2008 Page 102 of 948
REJ09B0177-0300