SH7059 Datasheet, PDF (132/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
Instruction
MOV.W @(disp,GBR),R0
MOV.L @(disp,GBR),R0
MOVA @(disp,PC),R0
MOVT Rn
SWAP.B Rm,Rn
SWAP.W Rm,Rn
XTRCT Rm,Rn
Instruction Code
11000101dddddddd
11000110dddddddd
11000111dddddddd
0000nnnn00101001
0110nnnnmmmm1000
0110nnnnmmmm1001
0010nnnnmmmm1101
Operation
(disp × 2 + GBR) → Sign
extension → R0
(disp × 4 + GBR) → R0
disp × 4 + PC → R0
T → Rn
Rm → Swap bottom two bytes
→ Rn
Rm → Swap two consecutive
words → Rn
Rm: Middle 32 bits of
Rn → Rn
Execution
Cycles
1
1
1
1
1
1
1
T Bit
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Rev.3.00 Mar. 12, 2008 Page 42 of 948
REJ09B0177-0300