SH7059 Datasheet, PDF (238/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Direct Memory Access Controller (DMAC)
CK
Internal
address
bus
Transfer
source
address
NOP
Indirect
address
Transfer
destination
address
Internal
data
bus
DMAC
indirect
address
buffer
DMAC
data
buffer
Indirect
address
NOP
Transfer
data
Indirect
address
Transfer data
Transfer data
Address
read cycle
(1st)
NOP
cycle
(2nd)
Data
read cycle
(3rd)
Data write cycle (4th)
Figure 10.7 Dual Address Mode and Indirect Address Transfer Timing Example 2
Internal Memory Space → Internal Memory Space
10.3.6 Bus Modes
Select the appropriate bus mode in the TM bits of CHCR0–CHCR3. There are two bus modes: cycle-steal and burst.
Cycle-Steal Mode: In cycle-steal mode, the bus right is given to another bus master after each one-transfer-unit (8-bit, 16-
bit, or 32-bit) DMAC transfer. When the next transfer request occurs, the bus right is obtained from the other bus master
and a transfer is performed for one transfer unit. When that transfer ends, the bus right is passed to the other bus master.
This is repeated until the transfer end conditions are satisfied.
Cycle-steal mode can be used with all categories of transfer destination, transfer source and transfer request. Figure 10.8
shows an example of DMA transfer timing in cycle-steal mode.
Bus control returned to CPU
Bus cycle
CPU
CPU CPU DMAC DMAC CPU DMAC DMAC CPU CPU
Read/Write
Read/Write
Figure 10.8 DMA Transfer Timing Example in Cycle-Steal Mode
Burst Mode: Once the bus right is obtained, transfer is performed continuously until the transfer end condition is
satisfied.
Rev.3.00 Mar. 12, 2008 Page 148 of 948
REJ09B0177-0300