SH7059 Datasheet, PDF (194/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. User Break Controller (UBC)
UBARH/UBARL
UBAMRH/UBAMRL
Internal address
bits 31–0
32
32
CP1 CP0
32
32
32
CPU cycle
DMA cycle
ID1 ID0
Instruction fetch
Data access
RW1 RW0
Read cycle
Write cycle
SZ1 SZ0
User
break
interrupt
Byte size
Word size
Longword size
UBID
Figure 8.2 Break Condition Judgment Method
8.3.2 Break on On-Chip Memory Instruction Fetch Cycle
On-chip memory (on-chip ROM and/or RAM) is always accessed as 32 bits in one bus cycle. Therefore, two instructions
can be retrieved in one bus cycle when fetching instructions from on-chip memory. At such times, only one bus cycle is
generated, but by setting the start addresses of both instructions in the user break address register (UBAR) it is possible to
cause independent breaks. In other words, when wanting to effect a break using the latter of two addresses retrieved in one
bus cycle, set the start address of that instruction in UBAR. The break will occur after execution of the former instruction.
Rev.3.00 Mar. 12, 2008 Page 104 of 948
REJ09B0177-0300