SH7059 Datasheet, PDF (591/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

18. A/D Converter
18.2.3 A/D Control Registers 0 to 2 (ADCR0 to ADCR2)
A/D control registers 0 to 2 (ADCR0 to ADCR2) are 8-bit readable/writable registers that control the start of A/D
conversion and selects the operating clock for A/D0 to A/D2.
ADCR0 to ADCR2 are initialized to H'0F by a power-on reset, and in hardware standby mode and software standby mode.
Bits 3 to 0 of ADCR0 to ADCR2 are reserved. These bits cannot be modified. These bits are always read as 1.
Bit:
7
6
5
4
3
2
1
0
TRGE
CKS
ADST
ADCS
—
—
—
—
Initial value:
0
0
0
0
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R
R
R
R
• Bit 7—Trigger Enable (TRGE): Enables or disables triggering of A/D conversion by external input or the ATU-II.
Bit 7:TRGE
0
1
Description
A/D conversion triggering by external input or ATU-II is disabled
A/D conversion triggering by external input or ATU-II is enabled
(Initial value)
For details of external or ATU-II trigger selection, see section 18.2.5, A/D Trigger Registers 0 to 2 (ADTRGR0 to
ADTRGR2).
When ATU triggering is selected, clear bit 7 of registers ADTRGR0 to ADTRGR2 to 0.
When external triggering is selected, upon input of the low level of a pulse to the ADTRG0 or ADTRG1 pin after
TRGE has been set to 1, the A/D converter detects the falling edge of a pulse and sets the ADST bit to 1 in ADCR. The
same operation is subsequently performed when 1 is written in the ADST bit by software. External triggering of A/D
conversion is only enabled when the ADST bit is cleared to 0.
When external triggering is used, the low level width of a pulse input to the ADTRG0 or ADTRG1 pin must be at least
1.5 Pφ clock cycles in width.
• Bit 6—Clock Select (CKS): Selects the A/D conversion time. A/D conversion is executed in a maximum of 266 states
when CKS is 0, and a maximum of 134 states when 1. To prevent incorrect operation, ensure that the ADST bit A/D
control registers 0 to 2 (ADCR0 to ADCR2) is cleared to 0 before changing the A/D conversion time. For details, see
section 18.4.3, Analog Input Sampling and A/D Conversion Time.
Bit 6:CKS
0
1
Description
Conversion time = 266 states (maximum)
Conversion time = 134 states (maximum)
(Initial value)
• Bit 5—A/D Start (ADST): Starts or stops A/D conversion. A/D conversion is started when ADST is set to 1, and
stopped when ADST is cleared to 0.
Bit 5:ADST
0
1
Description
A/D conversion is stopped
(Initial value)
A/D conversion is being executed
[Clearing conditions]
• Single mode: Automatically cleared to 0 when A/D conversion ends
• Scan mode: Automatically cleared to 0 on completion of one round of conversion on all
set channels (single-cycle scan)
Rev.3.00 Mar. 12, 2008 Page 501 of 948
REJ09B0177-0300