SH7059 Datasheet, PDF (23/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

SH7058 (Rev.3, REJ09B0046-0300H)
15.3.4 Synchronous Operation
Transmitting Serial Data (Synchronous Mode):
Figure 15.18 Sample Flowchart for Serial Transmitting
509
Differences between SH7058 and SH7058S/SH7059
SH7058S/SH7059
15.3.4 Synchronous Operation
Transmitting Serial Data (Synchronous Mode):
Figure 15.18 Sample Flowchart for Serial Transmitting
Figure amended and note added
Clear TE bit to 0 in SCR
Clear TE bit to 0 in SCR
4
Receiving Serial Data (Synchronous Mode):
Figure 15.20 Sample Flowchart for Serial Receiving (1)
511
Note: Do not write to SMR, SCR, BRR, or SDCR between
the start and the end of a transmit operation. However, this
does not apply to operation 4.
Receiving Serial Data (Synchronous Mode):
Figure 15.20 Sample Flowchart for Serial Receiving (1)
Figure amended and note added
Clear RE bit in SCR to 0
Clear RE bit in SCR to 0
5
Transmitting and Receiving Serial Data Simultaneously
(Synchronous Mode):
Figure 15.23 Sample Flowchart for Serial Transmission
and Reception
514
Note: Do not write to SMR, SCR, BRR, or SDCR between
the start and the end of a receive operation. However, this
does not apply to operation 5.
Transmitting and Receiving Serial Data Simultaneously
(Synchronous Mode):
Figure 15.23 Sample Flowchart for Serial Transmission
and Reception
Figure amended and notes added
Clear TE and RE bits in SCR to 0
Clear TE and RE bits in SCR to 0 6
16.4.2 Master Control Register_n (MCR_n) (n = 0, 1)
545
Bit 5: MCR5
Important: Usage of sleep mode is limited. Be sure to
carefully read section 16.8, Usage Notes.
16.4.3 General Status Register_n (GSR_n) (n = 0, 1)
550
Transmit/Receive Warning Flag
Indicates an error warning.
0: Reset condition: When TEC < 96, REC < 96, or TEC ≥
256
1: When 96 ≤ TEC < 256 or 96 ≤ REC
Note: Do not write to SMR, SCR, BRR, or SDCR between
the start and the end of a transmit/receive operation.
However, this does not apply to operation 6.
15.5.10 Note on Writing to Registers During Transmit,
Receive, and Transmit/Receive Operations
Newly added
Section 16 Synchronous Serial Communication Unit (SSU)
Newly added
17.4.2 Master Control Register_n (MCR_n) (n = 0, 1)
Description amended
Bit 5: MCR5
Note: Do not access to MB during sleep mode.
Certain restrictions apply when using sleep mode, Be sure
to read section 17.8, Usage Notes.
17.4.3 General Status Register_n (GSR_n) (n = 0, 1)
Description amended
Transmit/Receive Warning Flag
Indicates an error warning.
0: Reset condition: When TEC < 96, or REC < 96, or TEC ≥
256
1: When 96 ≤ TEC < 256 or 96 ≤ REC
Rev.3.00 Mar. 12, 2008 Page xxiii of xc
REJ09B0177-0300