SH7059 Datasheet, PDF (451/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Serial Communication Interface (SCI)
• Bit 4—Receive Enable (RE): Enables or disables the SCI serial receiver.
Bit 4: RE
0
1
Description
Receiver disabled
(Initial value)
Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER). These flags
retain their previous values.
Receiver enabled
Serial reception starts when a start bit is detected in asynchronous mode, or synchronous
clock input is detected in synchronous mode. Select the receive format in SMR before
setting RE to 1.
• Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE setting is
used only in asynchronous mode, and only if the multiprocessor mode bit (MP) in the serial mode register (SMR) is set
to 1 during reception. The MPIE setting is ignored in synchronous mode or when the MP bit is cleared to 0.
Bit 3: MPIE
0
Description
Multiprocessor interrupts are disabled (normal receive operation)
[Clearing conditions]
• When the MPIE bit is cleared to 0
• When data with MPB = 1 is received
(Initial value)
1
Multiprocessor interrupts are enabled. Receive-data-full interrupt requests (RXI), receive-
error interrupt requests (ERI), and setting of the RDRF, FER, and ORER status flags in the
serial status register (SSR) are disabled until data with the multiprocessor bit set to 1 is
received.
The SCI does not transfer receive data from RSR to RDR, does not detect receive errors,
and does not set the RDRF, FER, and ORER flags in the serial status register (SSR). When
it receives data that includes MPB = 1, MPB is set to 1, and the SCI automatically clears
MPIE to 0, generates RXI and ERI interrupts (if the TIE and RIE bits in SCR are set to 1),
and allows the FER and ORER bits to be set.
• Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if TDR
does not contain valid transmit data when the MSB is transmitted.
Bit 2: TEIE
Description
0
Transmit-end interrupt (TEI) requests are disabled*
(Initial value)
1
Transmit-end interrupt (TEI) requests are enabled*
Note: * The TEI request can be cleared by reading the TDRE bit in the serial status register (SSR) after it has been set
to 1, then clearing TDRE to 0 and clearing the transmit end (TEND) bit to 0; or by clearing the TEIE bit to 0.
Rev.3.00 Mar. 12, 2008 Page 361 of 948
REJ09B0177-0300