SH7059 Datasheet, PDF (538/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
Bit
Bit Name Initial Value R/W Description
3
IRR3
0
R/W Transmit Warning Interrupt Flag
This bit is set and latched if the transmit error counter (TEC) reaches a value
greater than 96. This bit is cleared by writing 1. Writing 0 is ignored. When
the interrupt is cleared, TEC still holds its value greater than 96.
0: Clearing condition: Writing 1
1: Error warning state caused by transmit error
Setting condition: When TEC ≥ 96
2
IRR2
0
R
Remote Frame Request Interrupt Flag
Indicates that a remote frame has been received in a mailbox. This bit is set
if at least one receive mailbox contains a remote frame transmission request.
This bit is cleared by ensuring all bits in the remote request wait register
(RFPR) are cleared. Writing to this bit is ignored.
0: Clearing condition: Clearing of all bits in RFPR
1: At least one remote request is waiting
Setting condition:
When a remote frame is received and the corresponding MBIMR = 0
1
IRR1
0
R
Receive Message Interrupt Flag
Indicates that there are waiting data frames received. If at least one receive
mailbox contains a waiting message, this bit is set. This bit is cleared when
all bits in the receive message waiting register (RXPR) are cleared, i.e. there
is no waiting message in any receive mailbox. A logical OR from each set
receive mailbox. Writing to this bit is ignored.
0: Clearing condition: Clearing of all bits in RXPR
1: Data frame received and stored in mailbox
Setting condition: When data is received and the corresponding MBIMR =
0
0
IRR0
1
R/W Reset/Halt/Sleep Interrupt Flag
Indicates that the CAN interface has been reset or halted and the HCAN is
now in configuration mode or in sleep mode.
An interrupt signal will be generated through this bit to notify the change of
the HCAN's state to the host CPU if an MCR0 (software reset), MCR1 (halt),
or MCR5 (sleep) request occurs. GSR can be read after this bit is set to
figure out which state the HCAN is in.
Important: When a sleep mode request needs to be made, halt mode
should be used beforehand. For details, see the MCR5 description.
0: Clearing condition: Writing 1
1: Transition to software reset mode, transition to halt mode, or transition to
sleep mode without halt mode
Setting condition: When reset/halt processing is completed after an MCR0
(software reset), MCR1 (halt), or MCR5 (sleep) is requested
Rev.3.00 Mar. 12, 2008 Page 448 of 948
REJ09B0177-0300