SH7059 Datasheet, PDF (80/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 12 Advanced Pulse Controller (APC) ................................................................................. 327
12.1 Overview................................................................................................................................................................ 327
12.1.1 Features..................................................................................................................................................... 327
12.1.2 Block Diagram.......................................................................................................................................... 328
12.1.3 Pin Configuration...................................................................................................................................... 329
12.1.4 Register Configuration.............................................................................................................................. 329
12.2 Register Descriptions ............................................................................................................................................. 329
12.2.1 Pulse Output Port Control Register (POPCR) .......................................................................................... 329
12.3 Operation ............................................................................................................................................................... 330
12.3.1 Overview................................................................................................................................................... 330
12.3.2 Advanced Pulse Controller Output Operation .......................................................................................... 331
12.4 Usage Notes ........................................................................................................................................................... 334
Section 13 Watchdog Timer (WDT) ................................................................................................ 335
13.1 Overview................................................................................................................................................................ 335
13.1.1 Features..................................................................................................................................................... 335
13.1.2 Block Diagram.......................................................................................................................................... 336
13.1.3 Pin Configuration...................................................................................................................................... 336
13.1.4 Register Configuration.............................................................................................................................. 337
13.2 Register Descriptions ............................................................................................................................................. 337
13.2.1 Timer Counter (TCNT)............................................................................................................................. 337
13.2.2 Timer Control/Status Register (TCSR)..................................................................................................... 337
13.2.3 Reset Control/Status Register (RSTCSR) ................................................................................................. 339
13.2.4 Register Access......................................................................................................................................... 339
13.3 Operation ............................................................................................................................................................... 340
13.3.1 Watchdog Timer Mode ............................................................................................................................. 340
13.3.2 Interval Timer Mode................................................................................................................................. 342
13.3.3 Timing of Setting the Overflow Flag (OVF) ............................................................................................ 342
13.3.4 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)............................................................. 342
13.4 Usage Notes ........................................................................................................................................................... 343
13.4.1 TCNT Write and Increment Contention ................................................................................................... 343
13.4.2 Changing CKS2 to CKS0 Bit Values ....................................................................................................... 343
13.4.3 Changing between Watchdog Timer/Interval Timer Modes..................................................................... 343
13.4.4 System Reset by WDTOVF Signal........................................................................................................... 344
13.4.5 Internal Reset in Watchdog Timer Mode.................................................................................................. 344
13.4.6 Manual Reset in Watchdog Timer ............................................................................................................ 344
Section 14 Compare Match Timer (CMT) ....................................................................................... 345
14.1 Overview................................................................................................................................................................ 345
14.1.1 Features..................................................................................................................................................... 345
14.1.2 Block Diagram.......................................................................................................................................... 345
14.1.3 Register Configuration.............................................................................................................................. 346
14.2 Register Descriptions ............................................................................................................................................. 346
14.2.1 Compare Match Timer Start Register (CMSTR) ...................................................................................... 346
14.2.2 Compare Match Timer Control/Status Register (CMCSR) ...................................................................... 347
14.2.3 Compare Match Timer Counter (CMCNT) .............................................................................................. 348
14.2.4 Compare Match Timer Constant Register (CMCOR)............................................................................... 348
14.3 Operation ............................................................................................................................................................... 349
14.3.1 Cyclic Count Operation ............................................................................................................................ 349
14.3.2 CMCNT Count Timing............................................................................................................................. 349
14.4 Interrupts................................................................................................................................................................ 349
14.4.1 Interrupt Sources and DTC Activation ..................................................................................................... 349
Rev.3.00 Mar. 12, 2008 Page lxxx of xc
REJ09B0177-0300