SH7059 Datasheet, PDF (527/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
Bit
Bit Name Initial Value R/W Description
15
TST7
0
R/W Test Mode
Enables/disables the test modes settable by TST[6:0]. When this bit is set,
the following TST[6:0] are enabled.
0: HCAN is in normal mode
1: HCAN is in test mode
14
TST6
0
R/W Write CAN Error Counters
Enables the TEC (transmit error counter) and REC (receive error counter) to
be writable. The same value is written to TEC and REC at the same time.
The maximum value that can be written to TEC and REC is D'255 (H'FF).
This means that the HCAN cannot be forced into the bus off state. Before
writing to TEC and REC, the HCAN needs to enter halt mode, and when
writing to TEC and REC, the TST7 bit (MCR15) should be set to 1. The
value written to TEC is used to write REC.
0: TEC/REC is not writable but read-only
1: TEC/REC is writable with the same value at the same time
13
TST5
0
R/W Forced Error Passive
Forces the HCAN to behave as an error passive node, regardless of the
error counters.
0: State of HCAN depends on error counters
1: HCAN behaves as an error passive node, regardless of error counters
12
TST4
0
R/W Automatic Acknowledge Mode
Allows the HCAN to generate its own acknowledge bit in order to enable the
self test. In order to enter self-test mode, the message transmitted needs to
be read back, and there are 2 settings for this. One is to set (Enable Internal
Loop = 1, Disable Tx Output = 1, and Disable Rx Input = 1), so that the Tx
value is internally provided to the Rx. The other way is to set (Enable Internal
Loop = 0, Disable Tx Output = 0, and Disable Rx Input = 0) and connect the
Tx and Rx onto the CAN bus so that the transmitted data can be received via
the CAN bus.
0: HCAN does not generate its own acknowledge bit
1: HCAN generates its own acknowledge bit
11
TST3
0
R/W Disable Error Counters
Enables/disables the error counters (TEC/REC). When this bit is disabled,
the error counters (TEC/REC) remain unchanged and retain the current
value. When this bit is enabled, the error counters (TEC/REC) operate
according to the CAN specification.
0: Error counters (TEC/REC) operate according to the CAN specification
1: Error counters (TEC/REC) remain unchanged and retain the current value
10
TST2
0
R/W Disable Rx Input
Controls the Rx to be supplied to the CAN Interface block. When this bit is
enabled, the Rx pin value is supplied to the CAN interface block. When this
bit is disabled, the Rx value for the CAN block is always retained or the Tx
value internally connected if Enable Internal Loop = 1.
0: Value of external Rx pin is supplied to the CAN interface block
1: Enable Internal Loop = 0: Rx value is retained for the CAN interface block
Enable Internal Loop = 1: Tx value is internally supplied to the CAN
interface block
Rev.3.00 Mar. 12, 2008 Page 437 of 948
REJ09B0177-0300