SH7059 Datasheet, PDF (335/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
11.2.8 Trigger Mode Register (TRGMDR)
The trigger mode register (TRGMDR) is an 8-bit register. The ATU-II has one TRGMDR register.
Bit:
7
6
5
4
3
2
1
0
TRGMD
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R
R
R
R
R
R
R
TRGMDR is an 8-bit readable/writable register that selects whether a channel 1 compare-match is used as a channel 8
one-shot pulse start trigger or as a one-shot pulse terminate trigger when channel 1 and channel 8 are used in combination.
TRGMDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode.
• Bit 7—Trigger Mode Selection Register (TRGMD): Selects the channel 8 one-shot pulse start trigger/one-shot pulse
terminate trigger setting.
Bit 7: TRGMD
0
1
Description
One-shot pulse start trigger (TCNT1B = OCR1)
One-shot pulse terminate trigger (TCNT1A = GR1A–GR1H)
One-shot pulse start trigger (TCNT1A = GR1A–GR1H)
One-shot pulse terminate trigger (TCNT1B = OCR1)
(Initial value)
• Bits 6 to 0—Reserved: These bits are always read as 0. The write value should always be 0.
11.2.9 Timer Mode Register (TMDR)
The timer mode register (TMDR) is an 8-bit register. The ATU-II has one TDR register.
Bit:
7
6
5
4
3
2
—
—
—
—
—
T5PWM
Initial value:
0
0
0
0
0
0
R/W:
R
R
R
R
R
R/W
1
T4PWM
0
R/W
0
T3PWM
0
R/W
TMDR is an 8-bit readable/writable register that specifies whether channels 3 to 5 are used in input capture/output
compare mode or PWM mode.
TMDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode.
• Bits 7 to 3—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 2—PWM Mode 5 (T5PWM): Selects whether channel 5 operates in input capture/output compare mode or PWM
mode.
Bit 2: T5PWM
0
1
Description
Channel 5 operates in input capture/output compare mode
Channel 5 operates in PWM mode
(Initial value)
Rev.3.00 Mar. 12, 2008 Page 245 of 948
REJ09B0177-0300