SH7059 Datasheet, PDF (214/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Bus State Controller (BSC)
T₁
T₂
T_idle
T₁
T₂
CK
Address
,
Data
CSn space read
Idle cycle
CSm space write
Figure 9.7 Idle Cycle Insertion Example
IW31 and IW30 specify the number of idle cycles required after a CS3 space read either to read other external spaces, or
for this chip, to perform write accesses. In the same manner, IW21 and IW20 specify the number of idle cycles after a CS2
space read, IW11 and IW10, the number after a CS1 space read, and IW01 and IW00, the number after a CS0 space read.
0 to 3 idle cycles can be specified.
9.4.2 Simplification of Bus Cycle Start Detection
For consecutive accesses to the same CS space, waits are inserted to provide the number of idle cycles designated by bits
CW3 to CW0 in BCR2. However, in the case of a write cycle after a read, the number of idle cycles inserted will be the
larger of the two values designated by the IW and CW bits. When idle cycles already exist between access cycles, waits
are not inserted. Figure 9.8 shows an example. A continuous access idle is specified for CSn space, and CSn space is
consecutively write-accessed.
Rev.3.00 Mar. 12, 2008 Page 124 of 948
REJ09B0177-0300