SH7059 Datasheet, PDF (187/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. User Break Controller (UBC)
Section 8 User Break Controller (UBC)
8.1 Overview
The user break controller (UBC) provides functions that simplify program debugging. Break conditions are set in the UBC
and a user break interrupt is generated according to the conditions of the bus cycle generated by the CPU or DMAC. This
function makes it easy to design an effective self-monitoring debugger, enabling the chip to easily debug programs
without using a large in-circuit emulator.
8.1.1 Features
The features of the user break controller are:
• The following break compare conditions can be set:
⎯ Address
⎯ CPU cycle/DMA cycle
⎯ Instruction fetch or data access
⎯ Read or write
⎯ Operand size: byte/word/longword
• User break interrupt generated upon satisfying break conditions
A user-designed user break interrupt exception processing routine can be run.
• Select either to break in the CPU instruction fetch cycle before the instruction is executed or after.
• Satisfaction of a break condition can be output to the UBCTRG pin.
Rev.3.00 Mar. 12, 2008 Page 97 of 948
REJ09B0177-0300