SH7059 Datasheet, PDF (120/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
Table 2.2 Sign Extension of Word Data
This LSI CPU
Description
Example of Conventional CPU
MOV.W
ADD
@(disp,PC),R1
R1,R0
.........
Data is sign-extended to 32 bits, and R1 becomes ADD.W #H'1234,R0
H'00001234. It is next operated upon by an ADD
instruction.
.DATA.W H'1234
Note: @(disp, PC) accesses the immediate data.
Load-Store Architecture: Basic operations are executed between registers. For operations that involve memory access,
data is loaded to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits,
however, are executed directly in memory.
Delayed Branch Instructions: Unconditional branch instructions are delayed branch instructions. With a delayed branch
instruction, the branch is taken after execution of the instruction following the delayed branch instruction. There are two
types of conditional branch instructions: delayed branch instructions and ordinary branch instructions.
Table 2.3 Delayed Branch Instructions
This LSI CPU
BRA
TRGET
ADD
R1,R0
Description
Executes the ADD before branching to TRGET.
Example of Conventional CPU
ADD.W R1,R0
BRA
TRGET
Multiply/Multiply-and-Accumulate Operations: 16-bit × 16-bit → 32-bit multiply operations are executed in one to
two cycles. 16-bit × 16-bit + 64-bit → 64-bit multiply-and-accumulate operations are executed in two to three cycles. 32-
bit × 32-bit → 64-bit multiply and 32-bit × 32-bit + 64bit → 64-bit multiply-and-accumulate operations are executed in
two to four cycles.
T Bit: The T bit in the status register changes according to the result of the comparison, and in turn is the condition
(true/false) that determines if the program will branch. The number of instructions that change the T bit is kept to a
minimum to improve the processing speed (table 2.4).
Table 2.4 T Bit
This LSI CPU
CMP/GE R1,R0
BT
TRGET0
BF
TRGET1
ADD
#1,R0
CMP/EQ #0,R0
BT
TRGET
Description
Example of Conventional CPU
T bit is set when R0 ≥ R1. The program branches
to TRGET0
when R0 ≥ R1 and to TRGET1 when R0 < R1.
CMP.W
BGE
BLT
R1,R0
TRGET0
TRGET1
T bit is not changed by ADD.
SUB.W #1,R0
T bit is set when R0 = 0. The program branches if _BEQ
R0 = 0.
TRGET
Immediate Data: Byte (8-bit) immediate data resides in the instruction code. Word or longword immediate data is not
input via instruction codes but is stored in a memory table. An immediate data transfer instruction (MOV) accesses the
memory table using the PC relative addressing mode with displacement (table 2.5).
Rev.3.00 Mar. 12, 2008 Page 30 of 948
REJ09B0177-0300